0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier

Toshikazu SUZUKI; Yoshinobu YAMAGAMI; Ichiro HATANAKA; Akinori SHIBAYAMA; Hironori AKAMATSU; Hiroyuki YAMAUCHI

doi:10.1093/ietele/e88-c.4.630

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier

Toshikazu SUZUKI, Yoshinobu YAMAGAMI, Ichiro HATANAKA, Akinori SHIBAYAMA, Hironori AKAMATSU, Hiroyuki YAMAUCHI

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This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V_dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V_dd above 0.5 V than those of using the control with logic-gate-delay. However, as V_dd is reduced below 0.5 V and gets close to the threshold voltage (V_th) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I_d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I_d) and V_th of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I_d and V_th is the prerequisite for the SRAM control in the range of V_dd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I_d and V_th for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V_dd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.630-638

Publication Date: 2005/04/01

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DOI: 10.1093/ietele/e88-c.4.630

Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)

Category: Memory

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Toshikazu SUZUKI, Yoshinobu YAMAGAMI, Ichiro HATANAKA, Akinori SHIBAYAMA, Hironori AKAMATSU, Hiroyuki YAMAUCHI, "0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 4, pp. 630-638, April 2005, doi: 10.1093/ietele/e88-c.4.630.
Abstract: This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V_dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V_dd above 0.5 V than those of using the control with logic-gate-delay. However, as V_dd is reduced below 0.5 V and gets close to the threshold voltage (V_th) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I_d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I_d) and V_th of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I_d and V_th is the prerequisite for the SRAM control in the range of V_dd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I_d and V_th for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V_dd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.630/_p

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@ARTICLE{e88-c_4_630,
author={Toshikazu SUZUKI, Yoshinobu YAMAGAMI, Ichiro HATANAKA, Akinori SHIBAYAMA, Hironori AKAMATSU, Hiroyuki YAMAUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier},
year={2005},
volume={E88-C},
number={4},
pages={630-638},
abstract={This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V_dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V_dd above 0.5 V than those of using the control with logic-gate-delay. However, as V_dd is reduced below 0.5 V and gets close to the threshold voltage (V_th) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I_d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I_d) and V_th of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I_d and V_th is the prerequisite for the SRAM control in the range of V_dd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I_d and V_th for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V_dd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.},
keywords={},
doi={10.1093/ietele/e88-c.4.630},
ISSN={},
month={April},}

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TY - JOUR
TI - 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier
T2 - IEICE TRANSACTIONS on Electronics
SP - 630
EP - 638
AU - Toshikazu SUZUKI
AU - Yoshinobu YAMAGAMI
AU - Ichiro HATANAKA
AU - Akinori SHIBAYAMA
AU - Hironori AKAMATSU
AU - Hiroyuki YAMAUCHI
PY - 2005
DO - 10.1093/ietele/e88-c.4.630
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V_dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V_dd above 0.5 V than those of using the control with logic-gate-delay. However, as V_dd is reduced below 0.5 V and gets close to the threshold voltage (V_th) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I_d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I_d) and V_th of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I_d and V_th is the prerequisite for the SRAM control in the range of V_dd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I_d and V_th for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V_dd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.
ER -