Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits
Summary :
Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.589-596
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.589
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Digital
Authors
Keyword
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Kenji SHIMAZAKI, Makoto NAGATA, Takeshi OKUMOTO, Shozo HIRANO, Hiroyuki TSUJIKAWA, "Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 589-596, April 2005, doi: 10.1093/ietele/e88-c.4.589.
Abstract: Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.589/_p
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@ARTICLE{e88-c_4_589,
author={Kenji SHIMAZAKI, Makoto NAGATA, Takeshi OKUMOTO, Shozo HIRANO, Hiroyuki TSUJIKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits},
year={2005},
volume={E88-C},
number={4},
pages={589-596},
abstract={Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.},
keywords={},
doi={10.1093/ietele/e88-c.4.589},
ISSN={},
month={April},}
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TY - JOUR
TI - Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 589
EP - 596
AU - Kenji SHIMAZAKI
AU - Makoto NAGATA
AU - Takeshi OKUMOTO
AU - Shozo HIRANO
AU - Hiroyuki TSUJIKAWA
PY - 2005
DO - 10.1093/ietele/e88-c.4.589
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.
ER -
English
