A new high ruggedness Power MOSFET structure with a planar oxide self align p+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p+ MASK process and contact p+ implant process. It is shown that the self align implant structure with a wide p+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p+ implant process is improved about 355% as compared to the traditional one.
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Feng-Tso CHIEN, Ming-Hung LAI, Shih-Tzung SU, Kou-Way TU, Ching-Ling CHENG, "High Ruggedness Power MOSFET Design by a Self-Align p+ Process" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 694-698, April 2005, doi: 10.1093/ietele/e88-c.4.694.
Abstract: A new high ruggedness Power MOSFET structure with a planar oxide self align p+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p+ MASK process and contact p+ implant process. It is shown that the self align implant structure with a wide p+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p+ implant process is improved about 355% as compared to the traditional one.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.694/_p
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@ARTICLE{e88-c_4_694,
author={Feng-Tso CHIEN, Ming-Hung LAI, Shih-Tzung SU, Kou-Way TU, Ching-Ling CHENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Ruggedness Power MOSFET Design by a Self-Align p+ Process},
year={2005},
volume={E88-C},
number={4},
pages={694-698},
abstract={A new high ruggedness Power MOSFET structure with a planar oxide self align p+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p+ MASK process and contact p+ implant process. It is shown that the self align implant structure with a wide p+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p+ implant process is improved about 355% as compared to the traditional one.},
keywords={},
doi={10.1093/ietele/e88-c.4.694},
ISSN={},
month={April},}
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TY - JOUR
TI - High Ruggedness Power MOSFET Design by a Self-Align p+ Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 694
EP - 698
AU - Feng-Tso CHIEN
AU - Ming-Hung LAI
AU - Shih-Tzung SU
AU - Kou-Way TU
AU - Ching-Ling CHENG
PY - 2005
DO - 10.1093/ietele/e88-c.4.694
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - A new high ruggedness Power MOSFET structure with a planar oxide self align p+ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p+ MASK process and contact p+ implant process. It is shown that the self align implant structure with a wide p+ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p+ implant process is improved about 355% as compared to the traditional one.
ER -