IEICE TRANSACTIONS on Electronics
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Summary :
We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.552-558
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.552
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Digital
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Keyword
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Kazutoshi KOBAYASHI, Masao ARAMOTO, Hidetoshi ONODERA, "A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 552-558, April 2005, doi: 10.1093/ietele/e88-c.4.552.
Abstract: We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.552/_p
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@ARTICLE{e88-c_4_552,
author={Kazutoshi KOBAYASHI, Masao ARAMOTO, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era},
year={2005},
volume={E88-C},
number={4},
pages={552-558},
abstract={We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.},
keywords={},
doi={10.1093/ietele/e88-c.4.552},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
T2 - IEICE TRANSACTIONS on Electronics
SP - 552
EP - 558
AU - Kazutoshi KOBAYASHI
AU - Masao ARAMOTO
AU - Hidetoshi ONODERA
PY - 2005
DO - 10.1093/ietele/e88-c.4.552
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.
ER -
English
