It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.

A new high-density dual-port DRAM architecture is proposed, which realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with the folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This new architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis on the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to a complete pipelining operation of DRAM array and a refresh-free DRAM core are also discussed.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.

This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.

Safety critical systems are often modeled using Time Petri Nets (TPN) for analyzing their reliability with formal verification methods. This paper proposed an efficient verification method for TPN introducing bounded model checking based on satisfiability solving. The proposed method expresses time constraints of TPN by Difference Logic (DL) and uses SMT solvers for verification. Its effectiveness was also demonstrated with an experiment.

This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.

A new source line routing architecture features a blanket-like source line made of double aluminum layers by utilizing a pure tungsten metal layer as the local interconnection layer in the peripheral region. The relaxed pitch of the signal lines improves the RC time delay constant of the signal lines and gives stable Vcc and Vss levels throughout the chip. Furthermore, this architecture brings about an 8% area reduction of the peripheral region in 256 Mb DRAMs with high performance,when used in collaboration with hierarchical bit-line architecture.

In low-voltage operating DRAM, one of the most serious problems is how to maintain the sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. This paper proposes a new array architecture called the Cell-plate line Connecting Complementary bit-line (C3) architecture which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliablity of the memory cell capacitor dielectric film. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6 3.2-µm2 cell size. This architecture will open the path for future battery-backup and/or battery-operating high-density DRAM's.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.

This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propose a novel testing methodology of the soft-error rate with a fast parallel multi-bit test. In addition, the proposed architecture resolves the critical problem of the look-up table maintenance of TCAM. The design techniques reported in this paper are especially attractive for realizing soft-error immune, high-performance TCAM chips.

The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability (@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 Cell/bit with the complementary dynamic memory operation and has the 1 Cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (Sense Synchronized Write) peripheral circuit technologies are also adopted for the low voltage and DFV (Dynamic Frequency and Voltage) controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

Various low power technologies have been developed and applied to LSIs from the point of device and circuit design. A lot more CPU cores as well as function IPs are integrated on a single chip LSI today. Therefore, not only the device and circuit low power technologies, but software power control technologies are becoming more important to reduce active power of application systems. This paper overviews the low power technologies and defines power management platform as a combination of hardware functions and software programming interface. This paper discusses importance of the power management platform and direction of its development.

A signature-matching co-processor in 130 nm CMOS technology for application in the network-security field is presented. Two key search technologies, implemented with fully-parallel CAM-based search cores, enable the removal of misused packets from Giga-bit-per-second (G-bps) networks in real-time without disturbing the normal network traffic. The first technology is a thorough search through packet header as well as payload in byte-shifting manner and is capable of detecting viruses, even if they are hidden at an arbitrary position within the packet. A 1.125 Mbit ternary CAM, operated at the speed of 125 Mega-searches per second (M-sps), integrates the primary lookup table for thorough packet search. The second technology applies an additional relational search with programmable logical operations to detect recently appearing more complicated misused packets. A small 192-bit binary CAM operated at 31.25 M-sps is also included for this purpose. Power dissipation, being a major concern of CAM-based application-specific LSIs, is addressed in the light of the signature-matching application, which has a high probability of multiple matches and which doesn't require to mask individual bits of the search word. Consequently, two application-driven power-reduction methods are implemented, namely an improved pipelined search for efficiently reducing power even in the case of a large number of multiple matches, and a search-line encoding for cutting search-line related power dissipation. As a result the signature-matching co-processor features low power dissipation between 0.4 W and 1.1 W for the best case and the worst case search configurations, respectively.

This paper reports an efficient Discrete Cosine Transform (DCT) processing method for images using a massive-parallel memory-embedded SIMD matrix processor. The matrix-processing engine has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. For compatibility with this matrix-processing architecture, the conventional DCT algorithm has been improved in arithmetic order and the vertical/horizontal-space 1 Dimensional (1D)-DCT processing has been further developed. Evaluation results of the matrix-engine-based DCT processing show that the necessary clock cycles per image block can be reduced by 87% in comprison to a conventional DSP architecture. The determined performances in MOPS and MOPS/mm2 are factors 8 and 5.6 better than with a conventional DSP, respectively.

This paper presents a novel optimized real-time Huffman encoder using a pipelined data path based on CAM technology and a parallel code-word-table optimizer. The exploitation of CAM technology enables fast parallel search of the code word table. At the same time, the code word table is optimized according to the frequency of received input symbols and is up-dated in real-time. Since these two functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. Evaluation results for the JPEG application show that the proposed architecture can achieve up to 28% smaller encoded picture sizes than the conventional architectures. The obtained encoding time can be reduced by 95% in comparison to a conventional SRAM-based architecture, which is suitable even for the latest end-user-devices requiring fast frame-rates. Furthermore, the proposed architecture provides the only encoder that can simultaneously realize small compressed data size and fast processing speed.

A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.

A Field Programmable Sequencer and Memory (FPSM), which is a programmable unit exclusively optimized for peripherals on a micro controller unit, is proposed. The FPSM functions as not only the peripherals but also the standard built-in memory. The FPSM provides easier programmability with a smaller area overhead, especially when compared with the FPGA. The FPSM is implemented on the FPGA and the programmability and performance for basic peripherals such as the 8 bit counter and 8 bit accuracy Pulse Width Modulation are emulated on the FPGA. Furthermore, the FPSM core with a 4K bit SRAM is fabricated in 0.18µm 5 metal CMOS process technology. The FPSM is an half the area of FPGA, its power consumption is less than one-fifth.

This paper describes a dual-mode sensing (DMS) scheme of a capacitor-coupled EEPROM cell. A new memory cell structure and a new sensing scheme are proposed and estimated. The new memory cell combines an EEPROM cell with a DRAM cell. The DMS Scheme utilizes the charge-mode sensing of the DRAM cell in addition to the current-mode sensing of the EEPROM cell. Using this DMS technique, the sensing speed can be enhanced by 36% at a cell current of 15 µA by virtue of the additional charge-mode sensing. Furthermore, the stress applied to the tunnel oxide of the memory transistor can be relieved by decreasing the programming voltage and shortening the programming time. Therefore, with this memory cell structure and sensing scheme, it is possible to realize high-speed sensing in low-voltage operation and high endurance.