IEICE TRANSACTIONS on Electronics
A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's
Summary :
A new high-density dual-port DRAM architecture is proposed, which realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with the folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This new architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis on the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to a complete pipelining operation of DRAM array and a refresh-free DRAM core are also discussed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.508-515
- Publication Date
- 1992/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
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Hideto HIDAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, "A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 4, pp. 508-515, April 1992, doi: .
Abstract: A new high-density dual-port DRAM architecture is proposed, which realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with the folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This new architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis on the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to a complete pipelining operation of DRAM array and a refresh-free DRAM core are also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_508/_p
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@ARTICLE{e75-c_4_508,
author={Hideto HIDAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's},
year={1992},
volume={E75-C},
number={4},
pages={508-515},
abstract={A new high-density dual-port DRAM architecture is proposed, which realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with the folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This new architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis on the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to a complete pipelining operation of DRAM array and a refresh-free DRAM core are also discussed.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 508
EP - 515
AU - Hideto HIDAKA
AU - Kazutami ARIMOTO
AU - Kazuyasu FUJISHIMA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - A new high-density dual-port DRAM architecture is proposed, which realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with the folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This new architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis on the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to a complete pipelining operation of DRAM array and a refresh-free DRAM core are also discussed.
ER -
English
