Limitations, innovations, and challenges of circuits and devices in silicon integrated circuits when they are scaled down to a half micrometer and smaller and reviewed. At the start, by examining physical limits of signal processing capabilities of a semiconductor device and power limits of circuits, the major directions of innovations are given. Then, device innovations in advanced MOSFET devices featuring sizes of a half micrometer, quarter micrometer, and even smaller than one tenth of a micrometer are reviewed. Circuit innovations in MOS VLSI's are also reviewed. Major issues are signal-to-noise ratio and speed of operation at low supply voltages. It is pointed out that miniaturized MOSFET's with channel lengths even shorter than one tenth of a micrometer could probably be realized with superior performance, but the circuit technique of using them at low-voltage power supplies still remains a challenge. Finally, it is pointed out that the real challenges in the future will be design and test limits of huge systems, and the real goals of engineers in the future will be functional integration rather than scale integration.

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-µm BiCMOS technology. A pair of ECL/CMOS level converters with build-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance.

The discrete cosine transform (DCT) has been recognized as one of the standard techniques in image compression. Therefore, a core processor which rapidly computes DCT has become a key component in image compression VLSI's. This paper describes a 100-MHz two-dimensional DCT core processor which is applicable to the real-time processing of HDTV signals. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with its sufficient accuracy satisfying the specifications in CCITT recommendation H.261. The core integrates about 102K transistors, and occupies 21 mm² using 0.8-µm double-metal CMOS technology.

In intelligent robots capable of autonomous work, the development of a high-performance special-purpose VLSI processor for collison detection will become very important for automatic motion planning. Conventionally, this kind of processing is performed by general-purpose processors. In this paper, a first collision detection VLSI processor is proposed to achieve ultrahigh-performance processing with an ideal parallel processing scheme. A large number of coordinate transformations and memory accesses to the obstacle memory are fully utilized in the processing algorithm, so that direct collision detection can be executed with a VLSI-oriented regular data flow. The structure of each processing element (PE) is very simple because a PE mainly consists of a COordinate Rotation DIgital Computer (CORDIC) arithmetic unit for the coordinate transformation and memories for the storage of manipulator and obstacle information. When 100 PE's are used to make parallel processing, the performance is about 10 000 times faster than that of conventional approaches using a single general-purpose microprocessor.

This paper describes a real-time degradable four-way set-associative cache memory control (CMC) LSI. Three kinds of errors, address parity error, comparator error, and multihit error, can cause functional degradation by killing the associative unit corresponding to the fault location. A 20-b tag parity generator, a double comparator, and a multihit detector are the key circuits for the fault detection. The parity generator and the double comparator have no effect on the timing-sensitive path delay because of the parallel configuration of the circuits. The multihit detector occupies about 16% of the propagation delay of the critical path, from the external address input to the hit/miss output.

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-µm CMOS EPROM process which includes an NVM module that provides the dedicated cells for the EPROM (10.6 µm²), PLD, and the configuration bits. The die size is 46 mm² (for PSD2, which contains 512-kb EPROM) and is housed in a 44-pin package. Memory access time through the PLD is 120 ns and the PLD pin-to-pin delay is 35 ns at 4.5 V and 75.

A multihighway serial/parallel (S/P) converter LSI chip suitable for the broad-band Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8-µm BiCMOS technology, handles 32-highway 8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF.

A high-performance CMOS line driver for ISDN U-interface transceiver applications has been designed and fabricated. Careful study of requirements and trade-offs affecting linearity, power efficiency, and quiescent current presented in this paper has resulted in a circuit structure featuring a highly linear input/output characteristic and well-controlled quiescent current. The prototype line driver is capable of delivering a 5V_pp signal of up to 80 kHz to a 60-Ω load while exhibiting linearity in the order of 77 5 dB and operating from a single 5-V power supply. Linearity better than 70 dB is maintained for load resistances as low as 20 Ω.

A two-terminal nonlinear element called a resistive fuse is described. Its application in image smoothing and segmentation is explained. Two types CMOS resistive fuses were designed, fabricated, and tested. The first implementation employs four depletion-mode NMOS and PMOS transistors, occupying a minimum area of 30 µm 38 µm. The second implementation uses 7 or 11 standard enhancement-mode transistors on an area of 75 µm 100 µm or less. Individual resistive-fuse circuits have been fabricated and tested and their functionality has been demonstrated. A one-dimensional network of 35 resistive fuses using the 11-transistor implementation was also fabricated in a standard CMOS process. Experimental results indicated that the network is capable of smoothing out small variations in image intensity while preserving the edges of objects.

A high-gain wide-band amplifier IC module is needed for high-speed communication systems. However, it is difficult to expand bandwidth and maintain stability. This is because small parasitic influences, such as bonding-wire inductance or the capacitance of the package, become large at high frequencies, thus degrading performance or causing parasitic oscillation. In this paper, a new design procedure is proposed for the high-gain and wide-band IC module, using stability analysis and a unified design methodology for IC's and packages. A multichip structure is developed using stability analysis and the requirements for stable operation are determined for each IC chip, package, and interface condition between them. Furthermore, to reduce the parasitic influences, several improvements in the interface and package design are clarified, such as wide-band matching and LC resonance damping. IC design using effective feedback techniques for enlarging the bandwidth are also presented. The IC's are fabricated using 0.2-µm GaAs MESFET IC technology. To verify the validity of these techniques, an equalizer IC module for 10-Gb/s optical communication systems was fabricated achieving a gain of 36 dB and a bandwidth of 9 GHz.

The paper presents an enhanced fully differential folded-cascode op-amp topology that achieves improved dc gain and common-mode rejection without sacrificing slew rate. The large-signal operation of the new topology is completely symmetric, providing equal positive and negative slew-rate behavior by making use of active current mirrors to bias the outputs rather than bias current sources as normally found in fully differential folded-cascode op amps. An additional advantage of the enhanced topology is that its common-mode output impedance is a factor of g_mr_o (typically 1-2 orders of magnitude) lower than the differential-mode output impedance, significantly improving the common-mode rejection ratio. The predicted performance is verified by simulations and preliminary experimental results.

This paper describes a dual-mode sensing (DMS) scheme of a capacitor-coupled EEPROM cell. A new memory cell structure and a new sensing scheme are proposed and estimated. The new memory cell combines an EEPROM cell with a DRAM cell. The DMS Scheme utilizes the charge-mode sensing of the DRAM cell in addition to the current-mode sensing of the EEPROM cell. Using this DMS technique, the sensing speed can be enhanced by 36% at a cell current of 15 µA by virtue of the additional charge-mode sensing. Furthermore, the stress applied to the tunnel oxide of the memory transistor can be relieved by decreasing the programming voltage and shortening the programming time. Therefore, with this memory cell structure and sensing scheme, it is possible to realize high-speed sensing in low-voltage operation and high endurance.

A 512-kb flash EEPROM developed for microcontroller applications will be reported. Many process and performance constraints associated with the conventional flash EEPROM have been eliminated through the development of a new flash EEPROM cell and new circuit techniques. Design of the 512-kb flash EEPROM, which is programmable for different array sizes, has been evaluated from 256- and 384-kb arrays embedded in new 32-b microcontrollers. The 512-kb flash EEPROM has incorporated the newly developed source-coupled split-gate (SCSG) flash EEPROM cell, Zener-diode controlled programming voltages, internally generated erase voltage, and a new differential sense amplifier. It has eliminated overerase and program disturb problems without relying on tight process controls and on critical operational sequences and timings, such as intelligent erase, intelligent program, and preprogram before erase. A modular approach was used for chip design to minimize development time and for processing technology to achieve high manufacturability and flexibility.

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

A 0.3-µm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: 1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability, and layout area; 2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; 3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and 4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed-DRAM's, based on the 4-Mb design.

In low-voltage operating DRAM, one of the most serious problems is how to maintain the sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. This paper proposes a new array architecture called the Cell-plate line Connecting Complementary bit-line (C³) architecture which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliablity of the memory cell capacitor dielectric film. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6 3.2-µm² cell size. This architecture will open the path for future battery-backup and/or battery-operating high-density DRAM's.

A Unique word-line voltage control method for the 64-Mb DRAM and beyond, which realizes a constant lifetime for thin gate oxide, is proposed. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps constant time-dependent dielectric breakdown (TDDB) lifetime, under any conditions concerning gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement, or a 0.3 1.8-V larger word-line voltage margin to write ONE data into the cell.

A new high-density dual-port DRAM architecture is proposed, which realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with the folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This new architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis on the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to a complete pipelining operation of DRAM array and a refresh-free DRAM core are also discussed.

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.

This paper presents novel temperature-compensation circuit techniques for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The abovementioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/. As a result, 6.5-ns faster RAS access time and improved latch-up immunity have been achieved, compared with conventional circuit techniques.

Two high-speed sensing techniques suitable for ultrahigh-speed SRAM's are proposed. These techniques can reduce a 64-kb SRAM access time to 71 89% of that of conventional high-speed bipolar SRAM's. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAM's for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 43% of conventional cells. A 64-kb SRAM with one of the sensing techniques is fabricated using 0.5-µm BiCMOS technology and achieves a 1.5-ns access time with a 78-µm² memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAM's, which have been used as cache and control memories of mainframe computers.

This paper describes a new biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSI's. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stage of signal amplification. Since feedback control of the ABC circuit ensures a correct dc biasing even under large process deviation and circuit condition changes, wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-µm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns.

An experimental 576K BiCMOS ECL-compatible SRAM that achieves 3.5-ns access and cycle is discussed. The SRAM is fully self-testable using less than 1K on-chip logic gates to assist characterization, wafer test, and package test. The I/O is also TTL programmable with the first-metal mask.

In this paper, we discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented, which uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than those of conventional carry select adders. The adder is integrated into an area of 0.41 3.36 mm² achieved by a 0.8-µm, triple-metal, full-CMOS process.

This paper presents a high-speed low power ac-coupled complementary push-pull ECL (AC-PP-ECL) circuit. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the base of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R_c from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8-µm double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/gate, the circuit offers 2.1 improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBT's, MESFET's, and Si BJT's. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. An 8:1 multiplexer and a 1:8 demultiplexer operating at 6 Gb/s and a 16:1 multiplexer and a 1:16 demultiplexer operating at 10 Gb/s were realized by HBT's and MESFET's, respectively. This paper describes Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2-Gb/s demultiplexer. These multigigabit LSI's have been mainly achieved by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f_max), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSI's are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding.

Relaxation-type monolithic silicon bipolar voltage-controlled oscillators (VCO's) with center frequencies ranging from 1.5 to 5 GHz are described. The maximum oscillating frequency achieved is 7.4 GHz. The VCO's dissipate about 70 mW from a 3.6-V supply, including the output buffer and voltage-to-current converter stages. Two types of on-chip timing capacitor structures and various configurations used in achieving these results are described. A wide tuning range has been achieved which is sufficient to cover the normal process tolerances and supply variations expected in a practical environment. The circuits are fabricated in an advanced 0.8-µm double-poly self-aligned bipolar technology.

Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.

An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.

This paper presents a pulsed sensing scheme with a limited bit-line swing designed for 4-Mb CMOS high-speed DRAM's (HSDRAM's) and beyond. It uses a standard CMOS cross-coupled sense amplifier and limits the swing by means of a pulsed sense clock. The signal loss that would occur if the bit-line swing was not exactly limited to one threshold above the word-line's low level is avoided by using a small reference voltage generator and trench decoupling capacitors. The new sensing scheme was successfully implemented on an experimental HSDRAM fabricated by using 0.7-µm L_eff CMOS technology, and thus a high-speed random access time of 15 ns and a low power dissipation of 144 mW were obtained for 512-kb array activation with a fast cycle time of 60 ns at 3.6 V.

The maximum bit capacity of poly-Si loaded SRAM's is estimated, based on cell stability limits. When SRAM density increases, the voltage level of a storage node in the high state decreases more quickly because of MOS drain leakage current that flows in the poly-Si load; this can prevent regular cell operation. The poly-Si load resistance and the drain leakage current distribution are measured by using special 0.8-µm 1-Mb SRAM test chips. The maximum bit capacity is then calculated for low-power and high-speed SRAM's. The limit is 4 Mb for low-power SRAM's and 4 Gb for high-speed SRAM's.