High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit

C. T. CHUANG; D. D. TANG

High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit

C. T. CHUANG, D. D. TANG

Full Text Views

0

Cite this

Summary :

This paper presents a high-speed low power ac-coupled complementary push-pull ECL (AC-PP-ECL) circuit. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the base of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R_c from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8-µm double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/gate, the circuit offers 2.1 improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.558-561

Publication Date: 1992/04/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

Category

Authors

C. T. CHUANG
D. D. TANG

Keyword

Cite this

Copy

C. T. CHUANG, D. D. TANG, "High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit" in IEICE TRANSACTIONS on Electronics, vol. E75-C, no. 4, pp. 558-561, April 1992, doi: .
Abstract: This paper presents a high-speed low power ac-coupled complementary push-pull ECL (AC-PP-ECL) circuit. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the base of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R_c from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8-µm double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/gate, the circuit offers 2.1 improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_558/_p

Copy

@ARTICLE{e75-c_4_558,
author={C. T. CHUANG, D. D. TANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit},
year={1992},
volume={E75-C},
number={4},
pages={558-561},
abstract={This paper presents a high-speed low power ac-coupled complementary push-pull ECL (AC-PP-ECL) circuit. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the base of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R_c from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8-µm double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/gate, the circuit offers 2.1 improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.},
keywords={},
doi={},
ISSN={},
month={April},}

Copy

TY - JOUR
TI - High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 558
EP - 561
AU - C. T. CHUANG
AU - D. D. TANG
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - This paper presents a high-speed low power ac-coupled complementary push-pull ECL (AC-PP-ECL) circuit. The circuit utilizes two capacitors to couple a transient voltage pulse from the common-emitter node of the switching transistors to the base of a pair of complementary p-n-p/n-p-n push-pull transistors to provide a large transient current during switching. In addition to a reduction of the power consumption and improvement in the pull-up and pull-down capability of the output stage, the circuit scheme completely decouples the collector load resistor R_c from the delay path, thus allowing a very small switching current to be used for the logic (current switch) stage without degrading the performance. Based on a 0.8-µm double-poly self-aligned complementary bipolar process at a power consumption of 0.5 mW/gate, the circuit offers 2.1 improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.
ER -