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Yoshikazu MIYAWAKI Takeshi NAKAYAMA Shin-ichi KOBAYASHI Natsuo AJIKA Makoto OHI Yasushi TERADA Hideaki ARIMA Tsutomu YOSHIHARA
To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.
Kazuo KOBAYASHI Yasushi TERADA Masanori HAYASHIKOSHI Takeshi NAKAYAMA Hideaki ARIMA Takayuki MATSUKAWA Tsutomu YOSHIHARA
High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm17 µm and the chip size is 57.2 mm3.75 mm. The address access time of 100 ns and the page read access time of 20 ns have been achieved. A nonvolatile CAM (Content Addressable Memory) cell will also be proposed.
Shin-ichi KOBAYASHI Hiroaki NAKAI Yuichi KUNORI Takeshi NAKAYAMA Yoshikazu MIYAWAKI Yasushi TERADA Hiroshi ONODA Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI Tsutomu YOSHIHARA
A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.81.6 µm2 and the chip measures 5.85.0 mm2. The divided bit line structure realizes a small NOR type memory cell.