1-2hit |
Kazuo KOBAYASHI Yasushi TERADA Masanori HAYASHIKOSHI Takeshi NAKAYAMA Hideaki ARIMA Takayuki MATSUKAWA Tsutomu YOSHIHARA
High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm17 µm and the chip size is 57.2 mm3.75 mm. The address access time of 100 ns and the page read access time of 20 ns have been achieved. A nonvolatile CAM (Content Addressable Memory) cell will also be proposed.
Katsuhiko NISHIMURA Kazuo KOBAYASHI
We propose a unique synchronous rectification method in the rectification circuit of a DC-DC converter. This paper describes a novel synchronous rectification circuit that uses a saturable current transformer. We explain operations of this circuit, and analyzed them in this work. In addition, we verified operations of this method applied in boost converter and demonstrated its effectiveness when two or more converters operate in parallel through simulations and experiments.