IEICE TRANSACTIONS on transactions
An Experimental 16 kbit Nonvolatile Random Access Memory
Summary :
High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm
- Publication
- IEICE TRANSACTIONS on transactions Vol.E73-E No.2 pp.260-264
- Publication Date
- 1990/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Kazuo KOBAYASHI
Yasushi TERADA
Masanori HAYASHIKOSHI
Takeshi NAKAYAMA
Hideaki ARIMA
Takayuki MATSUKAWA
Tsutomu YOSHIHARA
Keyword
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Kazuo KOBAYASHI, Yasushi TERADA, Masanori HAYASHIKOSHI, Takeshi NAKAYAMA, Hideaki ARIMA, Takayuki MATSUKAWA, Tsutomu YOSHIHARA, "An Experimental 16 kbit Nonvolatile Random Access Memory" in IEICE TRANSACTIONS on transactions,
vol. E73-E, no. 2, pp. 260-264, February 1990, doi: .
Abstract: High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e73-e_2_260/_p
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@ARTICLE{e73-e_2_260,
author={Kazuo KOBAYASHI, Yasushi TERADA, Masanori HAYASHIKOSHI, Takeshi NAKAYAMA, Hideaki ARIMA, Takayuki MATSUKAWA, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on transactions},
title={An Experimental 16 kbit Nonvolatile Random Access Memory},
year={1990},
volume={E73-E},
number={2},
pages={260-264},
abstract={High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - An Experimental 16 kbit Nonvolatile Random Access Memory
T2 - IEICE TRANSACTIONS on transactions
SP - 260
EP - 264
AU - Kazuo KOBAYASHI
AU - Yasushi TERADA
AU - Masanori HAYASHIKOSHI
AU - Takeshi NAKAYAMA
AU - Hideaki ARIMA
AU - Takayuki MATSUKAWA
AU - Tsutomu YOSHIHARA
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 2
JA - IEICE TRANSACTIONS on transactions
Y1 - February 1990
AB - High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm
ER -
English
