IEICE TRANSACTIONS on Electronics
Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory
Summary :
A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.784-790
- Publication Date
- 1994/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Category
Authors
Shin-ichi KOBAYASHI
Hiroaki NAKAI
Yuichi KUNORI
Takeshi NAKAYAMA
Yoshikazu MIYAWAKI
Yasushi TERADA
Hiroshi ONODA
Natsuo AJIKA
Masahiro HATANAKA
Hirokazu MIYOSHI
Tsutomu YOSHIHARA
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Shin-ichi KOBAYASHI, Hiroaki NAKAI, Yuichi KUNORI, Takeshi NAKAYAMA, Yoshikazu MIYAWAKI, Yasushi TERADA, Hiroshi ONODA, Natsuo AJIKA, Masahiro HATANAKA, Hirokazu MIYOSHI, Tsutomu YOSHIHARA, "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 5, pp. 784-790, May 1994, doi: .
Abstract: A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_784/_p
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@ARTICLE{e77-c_5_784,
author={Shin-ichi KOBAYASHI, Hiroaki NAKAI, Yuichi KUNORI, Takeshi NAKAYAMA, Yoshikazu MIYAWAKI, Yasushi TERADA, Hiroshi ONODA, Natsuo AJIKA, Masahiro HATANAKA, Hirokazu MIYOSHI, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory},
year={1994},
volume={E77-C},
number={5},
pages={784-790},
abstract={A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 784
EP - 790
AU - Shin-ichi KOBAYASHI
AU - Hiroaki NAKAI
AU - Yuichi KUNORI
AU - Takeshi NAKAYAMA
AU - Yoshikazu MIYAWAKI
AU - Yasushi TERADA
AU - Hiroshi ONODA
AU - Natsuo AJIKA
AU - Masahiro HATANAKA
AU - Hirokazu MIYOSHI
AU - Tsutomu YOSHIHARA
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8
ER -
English
