To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.81.6 µm2 and the chip measures 5.85.0 mm2. The divided bit line structure realizes a small NOR type memory cell.