A novel isolation structure which has a buried insulator between polysilicon electrodes (BIPS) has been developed. The BIPS isolation employs the refilling CVD-oxides in openings between polysilicon electrodes by photoresist etchback process. Device characteristics and parasitic effects of BIPS isolation have been compared with that of LOCOS isolation. Using BIPS isolation, we can almost suppress the narrow-channel effects and achieve the deep submicron isolation. No degradation on the subthreshold decay of devices with BIPS isolation can be obtained. The use of BIPS isolation technology yields a DRAM cell of small area. The successful fabrication of deep submicron devices with BIPS isolation clearly demonstrates that this technology has superior ability to overcome the LOCOS isolation.

A new method for the DRAM soft-error evaluation was developed. By using a focused proton microprobe as a radiation source, and scanning it on a memory cell plane, local sensitive structure of memory cells against soft-errors could be investigated with a form of the susceptibility mapping. Cell mode and bit-line mode soft-errors could be clearly distinguished by controlling the incident location and the proton dose, and it was also found that the incident beam within 4 µm around the monitored memory cell caused the soft-error. The retrograde well formed by the MeV ion implantation technology was examined by this method. It was confirmed that the B+ layers in the retrograde well were a sufficient barrier against the charge collection. The generation rate of the electron-hole pairs and the charge collection into n+ layers with a retrograde well and a conventional well were estimated by the device simulator, and were explained the experimental results.

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.81.6 µm2 and the chip measures 5.85.0 mm2. The divided bit line structure realizes a small NOR type memory cell.

SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.