Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's

Yasuo YAMAGUCHI; Toshiyuki OASHI; Takahisa EIMORI; Toshiaki IWAMATSU; Shouichi MITAMOTO; Katsuhiro SUMA; Takahiro TSURUDA; Fukashi MORISHITA; Masakazu HIROSE; Hideto HIDAKA; Kazutami ARIMOTO; Kazuyasu FUJISHIMA; Yasuo INOUE; Tadashi NISHIMURA; Hirokazu MIYOSHI

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's

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SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.772-780

Publication Date: 1996/06/25

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on ULSI Memory Technology)

Category: Dynamic RAMs

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Yasuo YAMAGUCHI, Toshiyuki OASHI, Takahisa EIMORI, Toshiaki IWAMATSU, Shouichi MITAMOTO, Katsuhiro SUMA, Takahiro TSURUDA, Fukashi MORISHITA, Masakazu HIROSE, Hideto HIDAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Yasuo INOUE, Tadashi NISHIMURA, Hirokazu MIYOSHI, "Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 6, pp. 772-780, June 1996, doi: .
Abstract: SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_772/_p

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@ARTICLE{e79-c_6_772,
author={Yasuo YAMAGUCHI, Toshiyuki OASHI, Takahisa EIMORI, Toshiaki IWAMATSU, Shouichi MITAMOTO, Katsuhiro SUMA, Takahiro TSURUDA, Fukashi MORISHITA, Masakazu HIROSE, Hideto HIDAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Yasuo INOUE, Tadashi NISHIMURA, Hirokazu MIYOSHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's},
year={1996},
volume={E79-C},
number={6},
pages={772-780},
abstract={SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 772
EP - 780
AU - Yasuo YAMAGUCHI
AU - Toshiyuki OASHI
AU - Takahisa EIMORI
AU - Toshiaki IWAMATSU
AU - Shouichi MITAMOTO
AU - Katsuhiro SUMA
AU - Takahiro TSURUDA
AU - Fukashi MORISHITA
AU - Masakazu HIROSE
AU - Hideto HIDAKA
AU - Kazutami ARIMOTO
AU - Kazuyasu FUJISHIMA
AU - Yasuo INOUE
AU - Tadashi NISHIMURA
AU - Hirokazu MIYOSHI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.
ER -