This parer describes high-speed CMOS SRAM circuit technologies used in cache memories. In recent years, high-speed SRAM technology has led to higher cycle frequencies, but the rate of increase in the SRAM density has slowed. Operating modes of high-speed SRAMs are compared and the advantage of wave-pipelined SRAMs in terms of cycle frequency is shown. Three types of sense amplifiers used in SRAMs are also compared from the viewpoint of speed and power dissipation. Current sense amplifiers provide high-speed operation with low power dissipation, while latch-type sense amplifiers appear most suitable for ultra-low-power SRAMs. Low voltage operation and size reduction of full CMOS cells are now the most pressing issues in the development of SRAMs for cache memories.

This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.

This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.

Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.

Low-power, high-speed match-detection circuits for a content addressable memory(CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns matchdetection time with 5-mW power dissipation in 10-ns cycle-time.

A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm² chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm²). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.

The effects of α-particle-induced parasitic bipolar current on soft errors in submicron 6-transistor SOI SRAMs were numericaly studied. It was shown that the bipolar current induces soft errors and that there exists a critical quantity which determines the soft error occurrence in the SOI SRAMs. Simulated soft error rates were in the same order as those for bulk SRAMs.

SOI DRAM's are candidates for giga-bit scale DRAM's due to the inherent features of SOI structure, and are also desired to be used as low-voltage memories which will be used in portable systems in the forthcoming multimedia era. However, some drawbacks are also anticipated owing to floating substrate effects. In this report, the advantages and problems concerning SOI DRAM's were reconsidered by evaluation of our test devices and also by analysis with device and circuit simulators for their future prospects. The following advantages of SOI DRAM's were verified. Low-voltage operation, active current reduction and speed gain were obtained by the reduced junction capacitance and the back-gate-bias effect. Static refresh characteristics were improved due to the reduced junction area. Soft error immunity was improved greatly by the complete isolation of the active region when the body potential is fixed. The problems that need to be resolved are closely related to the floating substrate effect. The soft error immunity in a floating body condition and the dynamic refresh characteristics were degraded by the instability of the floating body potential. Process and device approaches such as the field-shield-body-fixing method as well as circuit approaches like the BSG scheme are required to eliminate the floating substrate effects. From these investigations it can be said that a low-voltage DRAM with a current design rule would be possible if we pay close attention to the floating-substrate-related issues by optimizing various process/device and circuit techniques. With further development of the technology to suppress the floating substrate effects, it will be possible to develop simple and low-cost giga-bit level SOI DRAM's which use the SOI's inherent features to the full.

Stacked capacitor dynamic random access memory(DRAM) cells with both NMOS and PMOS cell transistors(Lg=0.4µm) were fabricated on ultra-thin SIMOX(separation by implantation of oxygen) substrates, and the data retention time was compared with that of a bulk counterpart. A DATA retention time of 550 sec(at 25 ) could be achieved using ultra-thin SIMOX substrates, which is 6 times longer than that using the bulk substrate. A stacked capacitor cell with a PMOS cell transistor on an ultra-thin SIMOX substrate is very attractive and promising for future giga-bit DRAM cells.

A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.

A 0.96µm² NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO₂ film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.

We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.

A new source line routing architecture features a blanket-like source line made of double aluminum layers by utilizing a pure tungsten metal layer as the local interconnection layer in the peripheral region. The relaxed pitch of the signal lines improves the RC time delay constant of the signal lines and gives stable V_cc and V_ss levels throughout the chip. Furthermore, this architecture brings about an 8% area reduction of the peripheral region in 256 Mb DRAMs with high performance,when used in collaboration with hierarchical bit-line architecture.

Ferroelectic nonvolatile technology comprises the ferroelectric material technology, the process technology and the circuit technology. Bi based layered Perovskyte ferroelectric material, SrBi₂Ta₂O₉, so called "Y 1," has superior characteristics in terms of endurance and nonvolatile properties, which is confirmed by a 256kbit ferroelectric nonvolatile memory. Critical issues regarding the ferroelectric process are reviewed. The lT/lC cell configuration which is essential for a high density memory and the reference voltage generator employed in the 256 k memory are described as is the architecture to reduce the power consumption of the memory.

A tunnel film(9 nm thick) formed by a rapid thermal oxidation in dry oxygen-rapid thermal nitridation in NH₃-rapid thermal oxynitridation in N₂O (ONN) sequence is applied to a stacked-gate flash memory cell, in which writing and erasing are carried out by Fowler-Nordheim tunneling at a drain and at a channel, respectively. The writing, erasing, endurance, disturbance and retention characteristics of the memory cells with ONN tunnel films are, for the first time, compared to those of the memory cells with conventional tunnel films such as dry oxide, N₂O-oxynitride and reoxidized nitrided oxide tunnel films. No significant difference of the writing and erasing characteristics was observed among the memory cells with the various tunnel films. However, the amount of V_th window narrowing in the endurance characteristics of the memory cells with ONN (-12.9%) and reoxidized nitrided oxide(-11.4%) tunnel films were much smaller than those of the memory cells with RTO(-34.0%) and NO (-38.2%) after 10⁶ write/erase cycles. Furthermore, the decrease in V_th in the drain disturbance characteristics of the memory cells with ONN tunnel films (21.2%) after weak electron-ejecting stress of 10⁵ cycles was smaller than those of the memory cells with the other films(51.4-64.4%). The retention characteristics of the memory cells with ONN tunnel films under the thermal stress of 200, 5.910⁵ sec were superior(ΔV_th=-2.1%) to those of the memory cells with the other films(ΔV_th=-5.4 - -8.2%). The reasons of these findings are because ONN films exhibit smaller number of charge traps and interface states induced by write/erase cycle stress, and suppress leakage curent stimulated by the weak electron-ejecting bias and the thermal stress, compared to the dry oxide, the N₂O-oxynitride and the reoxidized nitrided oxide. ONN films are found to be suitable for use as tunnel films of fiash memory cells.

A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70.

The data retention characteristics for Flash EEPROM degrade after a large number of write and erase cycles due to the increase of the tunnel oxide leakage current. This paper proposes a new write/erase method which uses a reverse polarity pulse after each erase pulse. By using this method, the leakage current can be suppressed. As a result, the read disturb time after 10⁵cycles write/erase operation is more than 10 times longer in comparison with that of the conventional method. Moreover, using this method, the endurance cycle dependence of the threshold voltage after write and erase operation is also drastically improved.

This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.

A copper(Cu) thick film conductor containing glass and metal oxide for aluminum niride(AlN) substrate was developed. The conductor showed adhesion strength and reliability which were almost comparable to those of Ag-Pd conductors and also had good solder wettability and erosion properties. The Cu conductors must be fired in a nitrogen atmosphere containing oxygen gas. When they were fired under a low oxygen concentration, the gasses thermally decomposed and their properties changed which meant that the molten gasses could not flow smoothly to the AlN surface, so adhesion strength decreased. On the other hand, under high oxygen concentration, the adhesion strength increased because the thermal decomposition and property changes were suppressed. However, poorer solder wettability was brought about because copper was oxidized. Metal oxide added to the conductor could improve the wettability without decreasing the adhesion strength, even if it was fired at the higher oxygen concentration. Suitable metal oxides were CdO, Co₃O₅ and Fe₂O₃.

The Michelson-interferometer (MI) optical resonator has been applied, together with physical interests, to a low pressure and slow-flow type CO₂ laser for specifying the system to a probe laser source. The fundamental characteristics online-selection, oscillation power and transverse mode are also investigated in comparison to the CO₂ laser obtained for various resonators such as an open-ended reflective-multiple interferometer (RMI), an open-sided MI, a Fox-Smith interferometer and soon. Consequently, it is confirmedthat the MI type laser proposed can be one of the promising scheme, without losing oscillation power much and transverse mode quality as a probe laser towards lineshape (or laser) parameter analysis. Translating one of the MI mirror by a slight distance on the order of a micron meter along the gain axis, we can not only switch either a single rotational-vibrational line or combination of multiple lines, but also obtain different combination of lines by translating a large amount of the translation distance of the order of 100 µm. Moreover, elimination of one of the side-mirrors in the MI resonator enables us to switch the oscillation lines at the expense of some output power.

We have investigated the gain and noise figure characteristics of a Nd-doped silica single-mode fiber amplifier (NDFA) at 1.06 µm which is applicable to various systems using a Nd: YAG laser light source at 1.06 µm, such as free-space laser communications, a fiber sensing system, and a lidar system. A fluorescence spectrum observation of the Nd-doped fibers with various co-dopants shows that the Nd-A1 co-doped fiber is suitable for realizing a high-gain amplifier for the 1.06-µm wavelength region. The pump wavelength tolerance at around 0.81 µm , the gain bandwidth and the sufficient value of the Nd concentration and length product for achieving maximum small signal gain are clarified. A noise figure of almost 3 dB and small signal gain of more than 30 dB are attained by 50-mW pump power. The unique four-level system characteristics, even in low pumppower conditions, provide low noise amplification in the NDFA. These gain and noise characteristics are well described by a simple theoretical model. We also demonstrated high-power operation of the NDFA with four pump LD modules adoptinga polarization-multiplexing technique. More than 100-mW signal output power is available for 1-mW signal input power at 200mW launched pump power. These features of the NDFA as a compact, polarization-independent, spatial-beam -distortion-free amplifier, will allow it to replace the solid sate laser in various applications using a Nd: YAG laser light source at 1.06µm.

The finite-difference beam-propagation method is applied to the analysis of a bent step-index slab optical waveguide. The results obtained in the rectangular coordinates with a modified index profile are compared with those in the cylindrical coordinates with a real index profile. It is found that the attenuation constant for TM_o mode is larger than that for TE_o mode. The polarization dependence of bending loss is negligible, provided the refractive index difference is less than 2%.