IEICE TRANSACTIONS on Electronics
NAND-Structured DRAM Cell with Lithography-Oriented Design
Summary :
A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.792-797
- Publication Date
- 1996/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on ULSI Memory Technology)
- Category
- Dynamic RAMs
Authors
Keyword
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Masami AOKI, Tohru OZAKI, Takashi YAMADA, Takeshi HAMAMOTO, "NAND-Structured DRAM Cell with Lithography-Oriented Design" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 6, pp. 792-797, June 1996, doi: .
Abstract: A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_792/_p
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@ARTICLE{e79-c_6_792,
author={Masami AOKI, Tohru OZAKI, Takashi YAMADA, Takeshi HAMAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={NAND-Structured DRAM Cell with Lithography-Oriented Design},
year={1996},
volume={E79-C},
number={6},
pages={792-797},
abstract={A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - NAND-Structured DRAM Cell with Lithography-Oriented Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 792
EP - 797
AU - Masami AOKI
AU - Tohru OZAKI
AU - Takashi YAMADA
AU - Takeshi HAMAMOTO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.
ER -
English
