New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.

NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm2, which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.

This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.

In the realization of Gigabit scale DRAM's, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecturte called cell-plate-line/bit-line complementary sensing(CBCS) architecture which realizes drastic array power reduction for both read/write operations and refersh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%. This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core diesign realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.

A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.

This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.