This letter reports a charge collection experiment of alpha-particle-induced carriers in the cell arrays of the 1 Mb DRAM. It is indicated that this experiment is effective to estimate the soft error rate of VLSI memories with various kinds of structures.

In low-voltage operating DRAM, one of the most serious problems is how to maintain the sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. This paper proposes a new array architecture called the Cell-plate line Connecting Complementary bit-line (C3) architecture which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliablity of the memory cell capacitor dielectric film. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6 3.2-µm2 cell size. This architecture will open the path for future battery-backup and/or battery-operating high-density DRAM's.

A multi-valued addressing scheme is proposed for a high speed, high packing density memory system. This scheme is a level-multiplex addressing scheme instead of standard time-multiplex addressing scheme, and provides all address signals to the DRAM at the same time without increasing the address pin counts. This scheme makes memory matrix strechable and achieves the low power dissipation using the enhanced partial array activation. The 16 Mb stretchable memory matrix DRAM (16MbSTDRAM) is examined using this addressing design. A power dissipation of 121.5 mW, access time of 30 ns, and 20 pin have been estimated for 3.3 v 16MbSTDRAM with X/Y=15/9 adress configuration. The low power battery-drive memory system for such as the note-book or the handheld-type personal computers can be realized by the STDRAMs with the multi-valued addressing scheme.

This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.

We propose an advanced DRAM array driving technique which can achieve low-voltage operation, which we call a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V Vcc. Therefore, we can make determining the Vth easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAM's with capacity of 256 Mbits and more.

This paper proposes a low voltage operation technique for a voltagedown converter(VDC) using a mixed-mode VDC(MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (LAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted to the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problpems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the ILVDC, can be applicable for both low voltage and high frequency operation.

We propose a smart design methodology for advanced ULSI memories to reduce the turn around time(TAT) for circuit revisions with no area penalty. This methodology was executed by distributing extra gate-arrays, which were composed of the n-channel and p-channel transistors, under the power line and the signal line. This method was applied to the development of a 16 Mb DRAM with double metal wiring. The design TAT can be reduced to 1/8 using 1500 gates. This design methodology has been confirmed to be very effective.

This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (Vth), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (VPP is below 2 VCC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.

In the realization of Gigabit scale DRAM's, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecturte called cell-plate-line/bit-line complementary sensing(CBCS) architecture which realizes drastic array power reduction for both read/write operations and refersh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%. This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core diesign realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.