This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.

An efficient back-bias (Vbb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a Vbb level of 1.44 V at Vcc1.5 V, compared to a conventional system in which Vbb only reaches 0.6 V. HPC can pump without the threshold voltage (Vth) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAM's, because a Vbb level lower than 1.0 V is necessary to meet the limitations of the Vth of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.

This paper proposes a low voltage operation technique for a voltagedown converter(VDC) using a mixed-mode VDC(MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (LAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted to the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problpems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the ILVDC, can be applicable for both low voltage and high frequency operation.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.

This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (Vth), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (VPP is below 2 VCC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.

This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.

We have newly developed a VLSI intelligent cache memory chip which constitutes one processor element of a Parallel Inference Machine (PIM/m) system. This cache memory chip contains 610 k transistors including 80 kbits memory cells. The chip measures 14.47 mm14.84 mm and is fabricated by using 1.0µm CMOS double metal technology. The cache memory chip implements a hardware support called "Trail Buffer" which is suitable for the execution of logic programming languages. We have determined the cache memory size by practical simulation taking the relationship between the chip size and hitratio of the cache memory into consideration. The scan test method and the special commands to access every memory cell are applied to enhance the testability. This chip itself operates at a cycle time of 30 MHz. The typical power consumption is 2.5 W with a 5.5 V power supply at 16.7 MHz operation. With this cache memory chip, the CPU board of the PIM/m is now tuned for 16.7 MHz operation and has attained 1.5 MLIPS (logical inference per second), which is the highest performance as an inference machine in the world.