IEICE TRANSACTIONS on Electronics
Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
Summary :
This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.858-865
- Publication Date
- 1995/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Tadaaki YAMAUCHI, Koji TANAKA, Kiyohiro FURUTANI, Yoshikazu MOROOKA, Hiroshi MIYAMOTO, Hideyuki OZAKI, "Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 7, pp. 858-865, July 1995, doi: .
Abstract: This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_7_858/_p
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@ARTICLE{e78-c_7_858,
author={Tadaaki YAMAUCHI, Koji TANAKA, Kiyohiro FURUTANI, Yoshikazu MOROOKA, Hiroshi MIYAMOTO, Hideyuki OZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs},
year={1995},
volume={E78-C},
number={7},
pages={858-865},
abstract={This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 858
EP - 865
AU - Tadaaki YAMAUCHI
AU - Koji TANAKA
AU - Kiyohiro FURUTANI
AU - Yoshikazu MOROOKA
AU - Hiroshi MIYAMOTO
AU - Hideyuki OZAKI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.
ER -
English
