In this paper, we evaluate the throughput performance of CDMA Slotted ALOHA systems. To improve the throughput performance, we employ the Quasi-synchronous sequences and the Modified Channel Load Sensing Protocol as an access control procedure. As a result, we found a good throughput by the QS-sequences. By employing MCLSP, we can keep the maximum throughput even in high offered load and in the presence of a long access timing delay, which is one of the issue in satellite packet communication systems.

The one of the problems in the satellite packet communication system is the existence of a long time delay, which may cause an improper packet access control resulting in a great deal of degradation of the system performance. In this paper, we clarify the effect of long time delay on the performance of CDMA ALOHA systems and then propose a new access control protocol, called Modified Channel Load Sensing Protocol (MCLSP), for the CDMA ALOHA systems. As a result, we show that a significant improvement in the throughput performance was obtained with MCLSP even in the presence of a long time delay.

Throughput analysis of CDMA Unslotted ALOHA with channel load sensing protocol (CLSP) is presented in consideration of the effect of the access timing delay. The access timing delay is defined as the sum of the process time and the propagation time for the packet access control. As CLSP is the scheme to control packet generation by the channel state information from the hub station, the effect of the access timing delay is significant. In our analysis, we extend a continuous-time Markov chain model and queueing systems. As a result, we found degradations of the throughput performance due to the access timing delay. For the value of CLSP threshold, we show that it is smaller than the case without the access timing delay in order to achieve satisfactory throughput. Furthermore, for a large access timing delay, CLSP makes no sense and the throughput is worse than the system without employing CLSP.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.