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Yasuhiko TSUKIKAWA Takeshi KAJIMOTO Yasuhiko OKASAKA Yoshikazu MOROOKA Kiyohiro FURUTANI Hiroshi MIYAMOTO Hideyuki OZAKI
An efficient back-bias (Vbb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a Vbb level of 1.44 V at Vcc1.5 V, compared to a conventional system in which Vbb only reaches 0.6 V. HPC can pump without the threshold voltage (Vth) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAM's, because a Vbb level lower than 1.0 V is necessary to meet the limitations of the Vth of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection.