IEICE TRANSACTIONS on Electronics
An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's
Summary :
This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (Vth), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (VPP is below 2 VCC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.719-727
- Publication Date
- 1995/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
- Category
Authors
Tsukasa OOISHI
Yuichiro KOMIYA
Kei HAMADE
Mikio ASAKURA
Kenichi YASUDA
Kiyohiro FURUTANI
Hideto HIDAKA
Hiroshi MIYAMOTO
Hideyuki OZAKI
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Tsukasa OOISHI, Yuichiro KOMIYA, Kei HAMADE, Mikio ASAKURA, Kenichi YASUDA, Kiyohiro FURUTANI, Hideto HIDAKA, Hiroshi MIYAMOTO, Hideyuki OZAKI, "An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 6, pp. 719-727, June 1995, doi: .
Abstract: This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (Vth), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (VPP is below 2 VCC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_6_719/_p
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@ARTICLE{e78-c_6_719,
author={Tsukasa OOISHI, Yuichiro KOMIYA, Kei HAMADE, Mikio ASAKURA, Kenichi YASUDA, Kiyohiro FURUTANI, Hideto HIDAKA, Hiroshi MIYAMOTO, Hideyuki OZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's},
year={1995},
volume={E78-C},
number={6},
pages={719-727},
abstract={This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (Vth), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (VPP is below 2 VCC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 719
EP - 727
AU - Tsukasa OOISHI
AU - Yuichiro KOMIYA
AU - Kei HAMADE
AU - Mikio ASAKURA
AU - Kenichi YASUDA
AU - Kiyohiro FURUTANI
AU - Hideto HIDAKA
AU - Hiroshi MIYAMOTO
AU - Hideyuki OZAKI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (Vth), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (VPP is below 2 VCC). They are applicable to the subquarter micron DRAM's of 256 Mb and more.
ER -
English
