IEICE TRANSACTIONS on Electronics
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories
Summary :
This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.2 pp.255-263
- Publication Date
- 2005/02/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.2.255
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Kiyohiro FURUTANI
Takeshi HAMAMOTO
Takeo MIKI
Masaya NAKANO
Takashi KONO
Shigeru KIKUDA
Yasuhiro KONISHI
Tsutomu YOSHIHARA
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kiyohiro FURUTANI, Takeshi HAMAMOTO, Takeo MIKI, Masaya NAKANO, Takashi KONO, Shigeru KIKUDA, Yasuhiro KONISHI, Tsutomu YOSHIHARA, "Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 2, pp. 255-263, February 2005, doi: 10.1093/ietele/e88-c.2.255.
Abstract: This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.2.255/_p
Copy
@ARTICLE{e88-c_2_255,
author={Kiyohiro FURUTANI, Takeshi HAMAMOTO, Takeo MIKI, Masaya NAKANO, Takashi KONO, Shigeru KIKUDA, Yasuhiro KONISHI, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories},
year={2005},
volume={E88-C},
number={2},
pages={255-263},
abstract={This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.},
keywords={},
doi={10.1093/ietele/e88-c.2.255},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 255
EP - 263
AU - Kiyohiro FURUTANI
AU - Takeshi HAMAMOTO
AU - Takeo MIKI
AU - Masaya NAKANO
AU - Takashi KONO
AU - Shigeru KIKUDA
AU - Yasuhiro KONISHI
AU - Tsutomu YOSHIHARA
PY - 2005
DO - 10.1093/ietele/e88-c.2.255
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2005
AB - This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.
ER -
English
