IEICE TRANSACTIONS on Electronics
A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs
Summary :
This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.4 pp.582-589
- Publication Date
- 1997/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- Category
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Kiyohiro FURUTANI, Tsukasa OOISHI, Mikio ASAKURA, Hideto HIDAKA, Hideyuki OZAKI, Michihiro YAMADA, "A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 4, pp. 582-589, April 1997, doi: .
Abstract: This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_4_582/_p
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@ARTICLE{e80-c_4_582,
author={Kiyohiro FURUTANI, Tsukasa OOISHI, Mikio ASAKURA, Hideto HIDAKA, Hideyuki OZAKI, Michihiro YAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs},
year={1997},
volume={E80-C},
number={4},
pages={582-589},
abstract={This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 582
EP - 589
AU - Kiyohiro FURUTANI
AU - Tsukasa OOISHI
AU - Mikio ASAKURA
AU - Hideto HIDAKA
AU - Hideyuki OZAKI
AU - Michihiro YAMADA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1997
AB - This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.
ER -
English
