A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories

Tadato YAMAGATA; Masaaki MIHARA; Takeshi HAMAMOTO; Yasumitsu MURAI; Toshifumi KOBAYASHI; Michihiro YAMADA; Hideyuki OZAKI

A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories

Tadato YAMAGATA, Masaaki MIHARA, Takeshi HAMAMOTO, Yasumitsu MURAI, Toshifumi KOBAYASHI, Michihiro YAMADA, Hideyuki OZAKI

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This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1657-1664

Publication Date: 1993/11/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)

Category: Application Specific Memory

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Tadato YAMAGATA, Masaaki MIHARA, Takeshi HAMAMOTO, Yasumitsu MURAI, Toshifumi KOBAYASHI, Michihiro YAMADA, Hideyuki OZAKI, "A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 11, pp. 1657-1664, November 1993, doi: .
Abstract: This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_11_1657/_p

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@ARTICLE{e76-c_11_1657,
author={Tadato YAMAGATA, Masaaki MIHARA, Takeshi HAMAMOTO, Yasumitsu MURAI, Toshifumi KOBAYASHI, Michihiro YAMADA, Hideyuki OZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories},
year={1993},
volume={E76-C},
number={11},
pages={1657-1664},
abstract={This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 1657
EP - 1664
AU - Tadato YAMAGATA
AU - Masaaki MIHARA
AU - Takeshi HAMAMOTO
AU - Yasumitsu MURAI
AU - Toshifumi KOBAYASHI
AU - Michihiro YAMADA
AU - Hideyuki OZAKI
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1993
AB - This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.
ER -