New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.

This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.

A new source line routing architecture features a blanket-like source line made of double aluminum layers by utilizing a pure tungsten metal layer as the local interconnection layer in the peripheral region. The relaxed pitch of the signal lines improves the RC time delay constant of the signal lines and gives stable Vcc and Vss levels throughout the chip. Furthermore, this architecture brings about an 8% area reduction of the peripheral region in 256 Mb DRAMs with high performance,when used in collaboration with hierarchical bit-line architecture.

The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.