Large Scale Embedded DRAM Technology
Summary :
The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E81-C No.5 pp.750-758
- Publication Date
- 1998/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
- Category
- DRAM
Authors
Keyword
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Akira YAMAZAKI, Tadato YAMAGATA, Yutaka ARITA, Makoto TANIGUCHI, Michihiro YAMADA, "Large Scale Embedded DRAM Technology" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 5, pp. 750-758, May 1998, doi: .
Abstract: The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_5_750/_p
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@ARTICLE{e81-c_5_750,
author={Akira YAMAZAKI, Tadato YAMAGATA, Yutaka ARITA, Makoto TANIGUCHI, Michihiro YAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Large Scale Embedded DRAM Technology},
year={1998},
volume={E81-C},
number={5},
pages={750-758},
abstract={The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Large Scale Embedded DRAM Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 750
EP - 758
AU - Akira YAMAZAKI
AU - Tadato YAMAGATA
AU - Yutaka ARITA
AU - Makoto TANIGUCHI
AU - Michihiro YAMADA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1998
AB - The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.
ER -
English
