111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method

Hirotoshi SATO; Shigeki OHBAYASHI; Yasuyuki OKAMOTO; Setsu KONDOH; Tomohisa WADA; Ryuuichi MATSUO; Michihiro YAMADA; Akihiko YASUOKA

111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method

Hirotoshi SATO, Shigeki OHBAYASHI, Yasuyuki OKAMOTO, Setsu KONDOH, Tomohisa WADA, Ryuuichi MATSUO, Michihiro YAMADA, Akihiko YASUOKA

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This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.735-742

Publication Date: 1996/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)

Category: Static RAMs

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Hirotoshi SATO, Shigeki OHBAYASHI, Yasuyuki OKAMOTO, Setsu KONDOH, Tomohisa WADA, Ryuuichi MATSUO, Michihiro YAMADA, Akihiko YASUOKA, "111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 6, pp. 735-742, June 1996, doi: .
Abstract: This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_735/_p

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@ARTICLE{e79-c_6_735,
author={Hirotoshi SATO, Shigeki OHBAYASHI, Yasuyuki OKAMOTO, Setsu KONDOH, Tomohisa WADA, Ryuuichi MATSUO, Michihiro YAMADA, Akihiko YASUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method},
year={1996},
volume={E79-C},
number={6},
pages={735-742},
abstract={This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - 111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
T2 - IEICE TRANSACTIONS on Electronics
SP - 735
EP - 742
AU - Hirotoshi SATO
AU - Shigeki OHBAYASHI
AU - Yasuyuki OKAMOTO
AU - Setsu KONDOH
AU - Tomohisa WADA
AU - Ryuuichi MATSUO
AU - Michihiro YAMADA
AU - Akihiko YASUOKA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.
ER -