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Tadahiko SUGIBAYASHI Takeshi HONDA Noboru SAKIMURA Shuichi TAHARA Naoki KASAI
Apart from magnetic random access memories (MRAM), nonvolatile memories cannot be used without causing fatigue. As the use of MRAMs can solve fatigue problems, MRAMs have a large potential to open up large new markets. The manufacturing cost of LSIs cannot be reduced while they have not been produced massively. To increase the size of the MRAM market, new applications, in which MRAMs create added value, are needed. A demo system that models a drive recorder was developed to introduce the novel features of MRAMs, and a 4-Mb MRAM was developed to be used in the demo system.
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA
This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.
Sadayuki OHKUMA Hiroshi ICHIKAWA Seigo YUKUTAKE Hitoshi ENDO Shuichi KUBOUCHI
A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm2 chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm2). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.