A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology

Sadayuki OHKUMA; Hiroshi ICHIKAWA; Seigo YUKUTAKE; Hitoshi ENDO; Shuichi KUBOUCHI

A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology

Sadayuki OHKUMA, Hiroshi ICHIKAWA, Seigo YUKUTAKE, Hitoshi ENDO, Shuichi KUBOUCHI

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A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm² chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm²). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.6 pp.763-766

Publication Date: 1996/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)

Category: Static RAMs

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Sadayuki OHKUMA, Hiroshi ICHIKAWA, Seigo YUKUTAKE, Hitoshi ENDO, Shuichi KUBOUCHI, "A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 6, pp. 763-766, June 1996, doi: .
Abstract: A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm² chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm²). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_6_763/_p

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@ARTICLE{e79-c_6_763,
author={Sadayuki OHKUMA, Hiroshi ICHIKAWA, Seigo YUKUTAKE, Hitoshi ENDO, Shuichi KUBOUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology},
year={1996},
volume={E79-C},
number={6},
pages={763-766},
abstract={A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm² chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm²). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 763
EP - 766
AU - Sadayuki OHKUMA
AU - Hiroshi ICHIKAWA
AU - Seigo YUKUTAKE
AU - Hitoshi ENDO
AU - Shuichi KUBOUCHI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1996
AB - A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm² chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm²). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.
ER -