Within the next few decades, high-end telecommunication systems on the larger nationwide network will require a switching capacity of over 5 Tbps. Advanced optical transmission technologies, such as wavelength division multiplexing (WDM) will support optical-fiber data transmission at such speeds. However, semiconductors may not be capable of high-throughput data switching because of the limitations by power consumption and operating speed, and pin count. Superconducting single flux quantum (SFQ) technology is a promising approach for overcoming these problems. This paper proposed an optical-electrical-SFQ hybrid switching system and a novel switch architecture. This architecture uses time-shifted internal speedup, shuffle and grouping exchange and a Batcher-Banyan switch. Our proposed switch consists of an interface circuit with small buffers, a Batcher sorter, a time-shift-speedup buffer (TSSB), a Banyan switch, and a slowdown buffer. Simulations showed good scalability up to 100 Tbps, which no router could ever offer such features.

We have studied an in situ edge preparation process and the effect of a substrate rotation during the edge preparation in order to improve the uniformity and electrical characteristics of high-Tc edge-type Josephson junctions. The improved YBa2Cu3Ox/PrBa2Cu3Ox/YBa2Cu3Ox edge junctions showed small 1σ-critical current spreads as low as 10% for 12 junctions. We have confirmed that the spreads do not increase significantly by adding groundplane over the junctions. In this paper, we will describe these processes developed for the fabrication of high-Tc superconducting integrated circuits.

Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.

Apart from magnetic random access memories (MRAM), nonvolatile memories cannot be used without causing fatigue. As the use of MRAMs can solve fatigue problems, MRAMs have a large potential to open up large new markets. The manufacturing cost of LSIs cannot be reduced while they have not been produced massively. To increase the size of the MRAM market, new applications, in which MRAMs create added value, are needed. A demo system that models a drive recorder was developed to introduce the novel features of MRAMs, and a 4-Mb MRAM was developed to be used in the demo system.

We describe the logic design of a single-flux-quantum (SFQ) 22 unit switch. It is the main component of the SFQ Banyan packet switch we are developing that enables a switching capacity of over 1 Tbit/s. In this paper, we focus on the design of the controller in the unit switch. The controller does not have a simple "off-the-shelf" conventional circuit, like those used in shift registers or adders. To design such a complicated random logic circuit, we need to adopt a systematic top-down design approach. Using a graphical technique, we first obtained logic functions. Next, to use the deep pipeline architecture, we broke down the functions into one-level logic operations that can be executed within one clock cycle. Finally, we mapped the functions on to the physical circuits using pre-designed SFQ standard cells. The 22 unit switch consists of 59 logic gates and needs about 600 Josephson junctions without gate interconnections. We tested the gate-level circuit by logic simulation and found that it operates correctly at a throughput of 40 GHz.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

Reentrant delay line memories using narrow YBa2Cu3O7-δ (YBCO) coplanar transmission lines are proposed. The proposed memory is composed of a looped YBCO coplanar delay line and a 22 semiconductor crossbar switch. This type of memory is superior to semiconductor memories in operating speed, the number of logic gates, power dissipation, and so on. We have also developed narrow and low-loss YBCO coplanar transmission lines for use in these reentrant delay line memories. Etch-back planarization and a patterning process combining Ar-ion milling and wet-etching enabled us to fabricate 18-cm-long YBCO coplanar transmission lines as narrow as 5 µm, and these lines did not suffer from electrical shorts even when the spacing was only 2. 5 µm. The surface resistances calculated from the attenuation constants of 5-, 10-, and 25-µm-wide lines provide similar low values of 0. 18-0. 26 mΩ at 10 GHz and 55 K. This indicates that the process damage was sufficiently suppressed despite the narrow line widths. The 5-µm-wide line attained a low attenuation constant of 2. 7 dB/m, which is similar to that in Cu coaxial cables. Even in the 5-µm-wide line, no significant increase in transmission loss was observed up to an input power level of 16 mW at 10 GHz and 55 K. This input power is comparable to that required to propagate digital signals from semiconductor circuits. Therefore high-speed digital signals can propagate through these narrow YBCO coplanar lines without significant attenuation of the signal pulses. Thus, these narrow YBCO coplanar lines can be used in the reentrant delay line memories.

In this paper, we describe our superconducting digital technology that uses Nb/AlOx/Nb Josephson junctions. Superconducting devices have intrinsically superior characteristics than those of semiconductor devices, and Nb/AlOx/Nb junctions have ideal current-voltage characteristics for digital applications. Superconducting devices that use Nb/AlOx/Nb junctions have being actively developed because of their high speed and low power characteristics. Presently, we can fabricate more than twenty thousand junctions on one chip. Using niobium technology, a superconducting 4-kbit RAM has been already successfully developed. We have demonstrated the operation of a network system with a superconducting network chip. Some problems, such as difficulty in high-speed testing, disturbance from trapped magnetic flux and so on, have been overcome by techniques such as a clock-driven testing method, moat structures and so on. The developed technologies, such as the fabrication technology, the design technology for moat structures and so on, must become the basic keys for the development of digital applications based on a single flux quantum device, which will be a promising component for ultra-high speed systems in the twenty-first century.

MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write failures from degrading 1 Gb MRAM yield where the standard deviation of magnetization-reversal current variation from other origins is less than 5%.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

We report the state of the art of superconducting network switching circuits and system technology. Mainly, we describe our switching core circuits and challenges to demonstrate superconducting prototype systems. And also, we review other approach to perform the superconducting digital communication briefly. In our switching core circuits, a ring-pipeline architecture has been proposed and the component circuits of the prototype chips have been fabricated and tested successfully. It is very important to demonstrate the prototype system in order to estimate the total performance of the system with superconducting devices. We have designed a multi-processor system with a superconducting network as a prototype system to demonstrate an interprocessor network system.

This is a review of our high-Tc superconductor (HTS) sampler development. The design and experimental demonstration of a Josephson sampler circuit based on YBa2 Cu3Ox(YBCO)/PrBa2Cu3Ox/YBCO ramp-edge junctions is described. The sampler circuit contains five edge junctions with a stacked YBCO groundplane and is based on single-flux quantum (SFQ) operations. Computer simulation results show that the time resolution of the sampler circuit depends strongly on the IcRn product of the junction and can be reduced to a few picoseconds with realistic parameter values. The edge junctions were fabricated using an in-situ process in which a barrier and a counter-electrode layer are deposited immediately after the edge etching without breaking the vacuum. The in-situ process improved the critical current uniformity of the junctions to 1σ20% in twelve 4-µm-width junctions. An YBCO groundplane was placed on the junctions in a multilayer structure we call the HUG (HTS cricuit with an upper-layer groundplane) structure. The inductance of YBCO lines was reduced to 1 pH per square without junction-quality degradation in the HUG structure. SFQ current-pulse generation, SFQ storage, and SFQ readout in the circuit have been confirmed by function tests using 3-kHz pulse currents. The successful operation of the sampler circuit has been demonstrated by measuring a signal-current waveform at 50K.