In this paper, we describe our superconducting digital technology that uses Nb/AlOx/Nb Josephson junctions. Superconducting devices have intrinsically superior characteristics than those of semiconductor devices, and Nb/AlOx/Nb junctions have ideal current-voltage characteristics for digital applications. Superconducting devices that use Nb/AlOx/Nb junctions have being actively developed because of their high speed and low power characteristics. Presently, we can fabricate more than twenty thousand junctions on one chip. Using niobium technology, a superconducting 4-kbit RAM has been already successfully developed. We have demonstrated the operation of a network system with a superconducting network chip. Some problems, such as difficulty in high-speed testing, disturbance from trapped magnetic flux and so on, have been overcome by techniques such as a clock-driven testing method, moat structures and so on. The developed technologies, such as the fabrication technology, the design technology for moat structures and so on, must become the basic keys for the development of digital applications based on a single flux quantum device, which will be a promising component for ultra-high speed systems in the twenty-first century.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

We report the state of the art of superconducting network switching circuits and system technology. Mainly, we describe our switching core circuits and challenges to demonstrate superconducting prototype systems. And also, we review other approach to perform the superconducting digital communication briefly. In our switching core circuits, a ring-pipeline architecture has been proposed and the component circuits of the prototype chips have been fabricated and tested successfully. It is very important to demonstrate the prototype system in order to estimate the total performance of the system with superconducting devices. We have designed a multi-processor system with a superconducting network as a prototype system to demonstrate an interprocessor network system.

Superconductive LSIs with Josephson junctions have features such as low power dissipation and high switching speed. In this paper, we review our developed 4-Kbit RAM with vortex transitional memory cells as an illustration of superconductive LSIs with Josephson junctions. We have developed a fabrication process technology for the 4-Kbit RAM. In the 4-Kbit RAM, 380ps access time and 9.8 mW power dissipation have been experimentally obtained. And also, we have estimated a suitable moat structure to reduce the influence of trapped magnetic structure. The 4-Kbit RAM has been successfully operated with a bit yield of 99.8%. Furthermore, we discuss GHz testing which is one of the most significant issues concerning superconductive digital LSIs.

To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 44 switch having block-to-block passive interconnections and a 22 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFQ circuits having passive interconnections.

We developed a 44 SFQ network switch prototype system and demonstrated its operation at 10 Gbps. The system's core is composed of two SFQ chips: a 44 switch and a 6-channel voltage driver. The 44 switch chip contained both a switch fabric (i.e. a data path) and a switch scheduler (i.e. a controller). Both chips were attached to a multi-chip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10 kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4 K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10 Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40 GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10 Gbps and found that it was on the order of 10-13 for the 44 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5 mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.

Within the next few decades, high-end telecommunication systems on the larger nationwide network will require a switching capacity of over 5 Tbps. Advanced optical transmission technologies, such as wavelength division multiplexing (WDM) will support optical-fiber data transmission at such speeds. However, semiconductors may not be capable of high-throughput data switching because of the limitations by power consumption and operating speed, and pin count. Superconducting single flux quantum (SFQ) technology is a promising approach for overcoming these problems. This paper proposed an optical-electrical-SFQ hybrid switching system and a novel switch architecture. This architecture uses time-shifted internal speedup, shuffle and grouping exchange and a Batcher-Banyan switch. Our proposed switch consists of an interface circuit with small buffers, a Batcher sorter, a time-shift-speedup buffer (TSSB), a Banyan switch, and a slowdown buffer. Simulations showed good scalability up to 100 Tbps, which no router could ever offer such features.

We describe the logic design of a single-flux-quantum (SFQ) 22 unit switch. It is the main component of the SFQ Banyan packet switch we are developing that enables a switching capacity of over 1 Tbit/s. In this paper, we focus on the design of the controller in the unit switch. The controller does not have a simple "off-the-shelf" conventional circuit, like those used in shift registers or adders. To design such a complicated random logic circuit, we need to adopt a systematic top-down design approach. Using a graphical technique, we first obtained logic functions. Next, to use the deep pipeline architecture, we broke down the functions into one-level logic operations that can be executed within one clock cycle. Finally, we mapped the functions on to the physical circuits using pre-designed SFQ standard cells. The 22 unit switch consists of 59 logic gates and needs about 600 Josephson junctions without gate interconnections. We tested the gate-level circuit by logic simulation and found that it operates correctly at a throughput of 40 GHz.

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40 GHz, and the demonstration of a 47-Gbps SFQ 22 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4 K with a two-stage 1-W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (~10 Gbps/ch) and SFQ circuits (>40 GHz). An SFQ 22 switch chip, in which the MUX/DEMUX and an SFQ 22 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10 kA/cm2. An SFQ 22 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with φ 50-µm InSn solder bumps. An SFQ 22 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47 Gbps for the first time.