We have studied the effect of Ga and Ca substitution in the PrBa2Cu3Oδ (PBCO) barrier on the parameters of high-temperature-superconductor ramp-edge Josephson junctions. Pr 1-XCa XBa2Cu3Oδ (X=0. 15, 0. 3) had reduced bulk barrier resistivity as small as 10 mΩcm which was close to the metal-insulator transition. Also, PrBa2Cu 3-ZGa ZOδ, written as GaZ-doped PBCO (Z=0. 15, 0. 3, 0. 6), had enhanced resistivity neater than 1 kΩcm at 4. 2 K. The transport mechanisms in these bulk barriers fitted well with the Mott variable hopping model. The critical current density Jc and normalized junction conductance (R nA)-1 decayed exponentially with almost the same decay length, as the barrier thickness increased. The decay length depended on the barrier material, and ranged from 1. 7 nm to 6. 5 nm for Jc, from 1. 9 nm to 7. 2 nm for (Rn A)-1. Because on these experimental results, we conclude that direct tunneling is the dominant transport mechanism for both quasi particles and paired particles in our junctions, while resonant tunneling should be considered as an additional transport mechanism of these two kinds of particles in the junctions with the PBCO-based barriers reported so far. It was also found that Ga doping raised the characteristic voltage Vc while Ca doping reduced it, though the Vc values obtained here were still small compared to the theoretically predicted values. The spacewise metal insulator transition at the interfaces caused by a high density of localized states in the barriers seemed to be responsible for the reduction in Vc. The best Vc value was 0. 32 mV at 77 K and 5. 2 mV at 4. 2 K using a Ga0. 6-PBCO barrier. These Vc values are suitable for electronics applications. Furthermore, superconducting-gap-like structures were observed in the junctions with highly resistive Ga-doped PBCO barriers.

We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.

We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be considered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimentally confirmed the correct operations of these circuits. The obtained bias margins were 33.1% for the HA and 24.6% for the CSSA.

We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40 GHz for an automatically routed 44 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.

To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 44 switch having block-to-block passive interconnections and a 22 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFQ circuits having passive interconnections.

We have developed a measuring system for high-Tc superconducting single-flux quantum circuits and evaluated its performance in terms of bit error rate (BER) measurement for given signal voltage levels. The system includes magnetic shields and a high-frequency test fixture mounted on a closed-cycle cooler. The test fixture is made of non-magnetic material. The transmission characteristics of the measuring system were evaluated by using a vector network analyzer at frequencies ranging from 40 MHz to 20 GHz. The operating temperature of the measuring system ranges from 20 K to room temperature. We connected a 12-GHz wideband pulse amplifier to the system and evaluated its high-speed transmission characteristics. We used a standard 50-Ω microstrip line as an impedance-matched sample. The signal used in the experiment was a 215-1 pseudo random bit signal (PRBS) at 3 Gbps. As a result, the output voltage required for an output driver under the experimental condition was 18.8 mV in order to obtain a resolution of BER measurement of 10-12.

We present a concept of an advanced rapid single-flux-quantum (RSFQ) logic circuit family using the combination of 0-shifted and π-shifted Josephson junctions. A π-shift in the current-phase relationship can be obtained in several types of Josephson junctions, such as Josephson junctions containing a ferromagnet barrier layer, depending on its thickness and temperature. We use a superconducting quantum interference devices composed of a pair of 0- and π-shifted Josephson junctions (0-π SQUIDs) as a basic circuit element. Unlike the conventional RSFQ logic, bistability is obtained by spontaneous circular currents without using a large superconductor loop, and the state can be flipped by smaller driving currents. These features lead to energy- and/or space-efficient logic gates. In this paper, we show several example circuits where we represent signals by flips of the states of a 0-π SQUID. We obtained successful operation of the circuits from numerical simulation.

A single flux quantum (SFQ) logic cell library has been developed for the 10 kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm2 to 10 kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

All MgB2 Josephson junctions with amorphous boron barriers have been fabricated on C-plane sapphire substrates by using a co-evaporation method. The junctions showed Josephson currents and the nonlinear current-voltage characteristics which seem to reflect the superconducting energy gap. The critical current was observed when the thickness of the amorphous boron was in the range of 5 nm to 20 nm. The critical current density was estimated to be 0.4 A/cm2 to 450 A/cm2. By observing he temperature dependence of the critical current we found that the junction had a critical temperature of 10 K and a normal layer in its barrier structure.

We describe three types of software-defined-radio (SDR) receivers based on superconducting technologies. The superconducting analog bandpass filters are essential for all types of the receivers. Another key component is an analog-to-digital converters (ADCs), which are required to have high resolution with a broad band width. The complementary Δ ADC based on the single-flux-quantum circuit is a promising candidate for the SDR receivers because it has a practical nature together with above-mentioned requirements. The experimentally obtained signal-to-noise ratio (SNR) and sensitivity, which are closely related to the resolution, are 34 dB and 20 µA for a quarter of the full-scale input with a band width of about 20 MHz. If we use the optimum decimation filter, the ADC is expected to have the SNR of 82 dB and the sensitivity of 300 nA. These values meet the requirements of the easiest type of the SDR receiver. After new fabrication process has been introduced and the architecture of the ADC has been improved, all types of recievers could be realized based on superconductors.

The single flux quantum (SFQ) is expected to be a next-generation high-speed and low-power technology in the field of logic circuits. CMOS as the dominant technology for conventional processors cannot be replaced with SFQ technology due to the difficulty of implementing feedback loops and conditional branches using SFQ circuits. This paper investigates the applicability of a reconfigurable data-path (RDP) accelerator based on SFQ circuits. The authors introduce detailed specifications of the SFQ-RDP architecture and compare its performance and power/performance ratio with those of a graphics-processing unit (GPU). The results show at most 1600 times higher efficiency in terms of Flops/W (floating-point operations per second/Watt) for some high-performance computing application programs.

We have studied the performances of several types of vortex flow transistors including prototype flux flow transistors (FFTs), nanobridge vortex flow transistors (NBVFTs) based on a parallel array of nanobridges, planar Josephson vortex flow transistors (planar JVFTs) based on a parallel array of grain boundary Josephson junctions, and JVFTs with a stacked structure (stacked JVFTs). The NBVFTs had considerably higher magnetic field sensitivity and shorter response time than the FFTs. A flux-to-voltage transfer function V/φ of 2.6 m V/φo and a modulation depth of 0.5 mV were obtained for the NBVFT composed of 2 nanobridges, while the current gain was small. The temperature dependence of the device parameters (the dynamic resistance and the inductance) suggests that the surface barrier to the Abrikosov vortex entry into the nanobridge strongly contributes to the relatively large V/φ values. The response time of the nanobridge is estimated to be 5 ps. On the other hand, the JVFTs showed large current gains because of the small kinetic inductance of the Josephson junction. The planar JVFT composed of 3 Josephson junctions with an asymmetrical geometry showed a current gain of 2.2 at 4.2 K. Also, the stacked JVFT showed the current gain of 2.0, while the maximum value of V/φ was 210 µV/φo. The mutual inductance between the control line and the superconducting loop within the transistor was enhanced in the stacked JVFT. This enhancement may yield a short response time compared to that of the planar JVFT. When we apply these vortex flow transistors, we should take account of the properties peculiar to each transistor.

We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.

We propose a desk-side supercomputer with large-scale reconfigurable data-paths (LSRDPs) using superconducting rapid single-flux-quantum (RSFQ) circuits. It has several sets of computing unit which consists of a general-purpose microprocessor, an LSRDP and a memory. An LSRDP consists of a lot of, e.g., a few thousand, floating-point units (FPUs) and operand routing networks (ORNs) which connect the FPUs. We reconfigure the LSRDP to fit a computation, i.e., a group of floating-point operations, which appears in a 'for' loop of numerical programs by setting the route in ORNs before the execution of the loop. We propose to implement the LSRDPs by RSFQ circuits. The processors and the memories can be implemented by semiconductor technology. We expect that a 10 TFLOPS supercomputer, as well as a refrigerating engine, will be housed in a desk-side rack, using a near-future RSFQ process technology, such as 0.35 µm process.

We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.

We have studied on thermally assisted nano-structured transistors made of superconductor ultra-thin films. These transistors potentially work as interface devices for Josephson-CMOS (complementary metal oxide semiconductor) hybrid memory systems, because they can generate a high output voltage of sub-V enough to drive a CMOS transistor. In addition, our superconductor transistors are formed with very fine lines down to several tens of nm in widths, leading to very small foot print enabling us to make large capacity hybrid memories. Our superconductor transistors are made with niobium titanium nitride (NbTiN) thin films deposited on thermally-oxidized silicon substrates, on which other superconductor circuits or semiconductor circuits can be formed. The NbTiN thickness dependence of the critical temperature and of resistivity suggest thermally activated vortex or anti-vortex behavior in pseudo-two-dimensional superconducting films plays an important role for the operating principle of the transistors. To show the potential that the transistors can drive MOS transistors, we analyzed the driving ability of the superconductor transistors with HSPICE simulation. We also showed the turn-on behavior of a MOS transistor used for readout of a CMOS memory cell experimentally. These results showed the high potential of superconductor transistors for Josephson-CMOS hybrid memories.

We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4 mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

One of the fundamental problems in many-pixel detectors implemented in cryogenics environments is the number of bias and read-out wires. If one targets a megapixel range detector, number of wires should be significantly reduced. One possibility is that the detectors are serially connected and biased by using only one line and read-out is accomplished by on-chip circuitry. In addition to the number of pixels, the detectors should have fast response times, low dead times, high sensitivities, low inter-pixel crosstalk and ability to respond to simultaneous irradiations to individual pixels for practical purposes. We have developed an equivalent circuit model for a serially connected superconducting strip line detector (SSLD) array together with the read-out electronics. In the model we take into account the capacitive effects due to the ground plane under the detector, effects of the shunt resistors fabricated under the SSLD layer, low pass filters placed between the individual pixels that enable individual operation of each pixel and series resistors that prevents the DC bias current flowing to the read-out electronics as well as adjust the time constants of the inductive SSLD loop. We explain the results of investigation of the following parameters: Crosstalk between the neighbor pixels, response to simultaneous irradiation, dead times, L/R time constants, low pass filters, and integration with the SFQ front-end circuit. Based on the simulation results, we show that SSLDs are promising devices for detecting a wide range of incident radiation such as neurons, X-rays and THz waves in many-pixel configurations.