IEICE TRANSACTIONS on Electronics
Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
Summary :
We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E104-C No.9 pp.435-445
- Publication Date
- 2021/09/01
- Publicized
- 2021/03/17
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2020SUP0001
- Type of Manuscript
- Special Section PAPER (Special Section on Fabrication of Superconductor Devices; Key Technology in Superconductor Electronics)
- Category
Authors
Shuichi NAGASAWA
AIST
Masamitsu TANAKA
Nagoya University
Naoki TAKEUCHI
Yokohama National University
Yuki YAMANASHI
Yokohama National University
Shigeyuki MIYAJIMA
NICT
Fumihiro CHINA
NICT
Taiki YAMAE
Yokohama National University
Koki YAMAZAKI
University of Electro-Communica-tions
Yuta SOMEI
University of Electro-Communica-tions
Naonori SEGA
University of Electro-Communica-tions
Yoshinao MIZUGAKI
University of Electro-Communica-tions
Hiroaki MYOREN
Saitama University
Hirotaka TERAI
NICT
Mutsuo HIDAKA
AIST
Nobuyuki YOSHIKAWA
Yokohama National University
Akira FUJIMAKI
Nagoya University
Keyword
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Shuichi NAGASAWA, Masamitsu TANAKA, Naoki TAKEUCHI, Yuki YAMANASHI, Shigeyuki MIYAJIMA, Fumihiro CHINA, Taiki YAMAE, Koki YAMAZAKI, Yuta SOMEI, Naonori SEGA, Yoshinao MIZUGAKI, Hiroaki MYOREN, Hirotaka TERAI, Mutsuo HIDAKA, Nobuyuki YOSHIKAWA, Akira FUJIMAKI, "Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 9, pp. 435-445, September 2021, doi: 10.1587/transele.2020SUP0001.
Abstract: We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020SUP0001/_p
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@ARTICLE{e104-c_9_435,
author={Shuichi NAGASAWA, Masamitsu TANAKA, Naoki TAKEUCHI, Yuki YAMANASHI, Shigeyuki MIYAJIMA, Fumihiro CHINA, Taiki YAMAE, Koki YAMAZAKI, Yuta SOMEI, Naonori SEGA, Yoshinao MIZUGAKI, Hiroaki MYOREN, Hirotaka TERAI, Mutsuo HIDAKA, Nobuyuki YOSHIKAWA, Akira FUJIMAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation},
year={2021},
volume={E104-C},
number={9},
pages={435-445},
abstract={We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.},
keywords={},
doi={10.1587/transele.2020SUP0001},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
T2 - IEICE TRANSACTIONS on Electronics
SP - 435
EP - 445
AU - Shuichi NAGASAWA
AU - Masamitsu TANAKA
AU - Naoki TAKEUCHI
AU - Yuki YAMANASHI
AU - Shigeyuki MIYAJIMA
AU - Fumihiro CHINA
AU - Taiki YAMAE
AU - Koki YAMAZAKI
AU - Yuta SOMEI
AU - Naonori SEGA
AU - Yoshinao MIZUGAKI
AU - Hiroaki MYOREN
AU - Hirotaka TERAI
AU - Mutsuo HIDAKA
AU - Nobuyuki YOSHIKAWA
AU - Akira FUJIMAKI
PY - 2021
DO - 10.1587/transele.2020SUP0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2021
AB - We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.
ER -
English
