We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be considered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimentally confirmed the correct operations of these circuits. The obtained bias margins were 33.1% for the HA and 24.6% for the CSSA.

We describe three types of software-defined-radio (SDR) receivers based on superconducting technologies. The superconducting analog bandpass filters are essential for all types of the receivers. Another key component is an analog-to-digital converters (ADCs), which are required to have high resolution with a broad band width. The complementary Δ ADC based on the single-flux-quantum circuit is a promising candidate for the SDR receivers because it has a practical nature together with above-mentioned requirements. The experimentally obtained signal-to-noise ratio (SNR) and sensitivity, which are closely related to the resolution, are 34 dB and 20 µA for a quarter of the full-scale input with a band width of about 20 MHz. If we use the optimum decimation filter, the ADC is expected to have the SNR of 82 dB and the sensitivity of 300 nA. These values meet the requirements of the easiest type of the SDR receiver. After new fabrication process has been introduced and the architecture of the ADC has been improved, all types of recievers could be realized based on superconductors.