This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase generator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9-2.15Gbps continuous rate. It consumes 5.1-8.4mA in its active state and 42μA leakage current in its stand-by state from a 1.0V supply.

A 32-bit arithmetic logic unit (ALU) is designed for a rapid single flux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D flip flops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the effectiveness of using clockless gates in wide datapath circuits.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic device. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, and several low-latency AQFP logic gates have been demonstrated. In delay-line clocking, the latency between adjacent excitation phases is determined by the propagation delay of excitation currents, and thus the rising time of excitation currents should be sufficiently small; otherwise, an AQFP gate can switch before the previous gate is fully excited. This means that delay-line clocking needs high clock frequencies, because typical excitation currents are sinusoidal and the rising time depends on the frequency. However, AQFP circuits need to be tested in a wide frequency range experimentally. Hence, in the present study, we investigate AQFP circuits adopting delay-line clocking with square excitation currents to apply delay-line clocking in a low frequency range. Square excitation currents have shorter rising time than sinusoidal excitation currents and thus enable low frequency operation. We demonstrate an AQFP buffer chain with delay-line clocking using square excitation currents, in which the latency is approximately 20ps per gate, and confirm that the operating margin for the buffer chain is kept sufficiently wide at clock frequencies below 1GHz, whereas in the sinusoidal case the operating margin shrinks below 500MHz. These results indicate that AQFP circuits adopting delay-line clocking can operate in a low frequency range by using square excitation currents.

Deep learning applications have often been processed in the cloud or on servers. Still, for applications that require privacy protection and real-time processing, the execution environment is moved to edge devices. Edge devices that implement a neural network (NN) are physically accessible to an attacker. Therefore, physical attacks are a risk. Fault attacks on these devices are capable of misleading classification results and can lead to serious accidents. Therefore, we focus on the softmax function and evaluate a fault attack using a clock glitch against NN implemented in an 8-bit microcontroller. The clock glitch is used for fault injection, and the injection timing is controlled by monitoring the power waveform. The specific waveform is enrolled in advance, and the glitch timing pulse is generated by the sum of absolute difference (SAD) matching algorithm. Misclassification can be achieved by appropriately injecting glitches triggered by pattern detection. We propose a countermeasure against fault injection attacks that utilizes the randomization of power waveforms. The SAD matching is disabled by random number initialization on the summation register of the softmax function.

This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.

With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

This letter reveals that an edge-triggered master-slave flip-flop (FF) using well-known soft error tolerant DICE (dual interlocked storage cell) is vulnerable to soft errors occurring around clock edge. This letter presents a design of a soft error tolerant FF based on the master-slave FF using DICE. The proposed design modifies the connection between the master and slave latches to make the FF not vulnerable to these errors. The hardware overhead is almost the same as that for the original edge-triggered FF using the DICE.

In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.

We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

A novel spur cancelled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs that degrade RX sensitivities are canceled by applying the SCCG to digital circuits or ADCs. The SCCG is integrated into a Bluetooth Low Energy (BLE) SoC fabricated in a 65 nm CMOS process. A measured clock spur reduction of 34 dB and an RX sensitivity recovery of 5 dB are achieved by the proposed SCCG. The power consumption and occupied area of the SCCG is only 18 µW and 40 μm × 120 μm, respectively.

An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.

A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18µm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65µm × 75µm and consumes 1.1mW with the power supply of 1.8V. Temperature coefficient (TC) is 69.5ppm/°C from 0 to 100°C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192MHz within 12.67k-hits. At 192MHz, it shows a 1-MHz-offset phase noise of -102dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.

As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power-safety without significant test vector count inflation and test quality loss.

This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

A network-based remote host clock skew measurement involves collecting the offsets, the differences between sending and receiving times, of packets from the host within a period of time. Although the variant and immeasurable delay in each packet prevents the measurer from getting the real clock offset, the local minimum delays and the majority of delays delineate the clock offset shifts, and are used by existing approaches to estimate the skew. However, events during skew measurement like time synchronization and rerouting caused by switching network interface or base transceiver station may break the trend into multi-segment patterns. Although the skew in each segment is theoretically of the same value, the skew derived from the whole offset-set usually differs with an error of unpredictable scale. In this work, a method called dynamic region of offset majority locating (DROML) is developed to detect multi-segment cases, and to precisely estimate the skew. DROML is designed to work in real-time, and it uses a modified version of the HT-based method [8] both to measure the skew of one segment and to detect the break between adjacent segments. In the evaluation section, the modified HT-based method is compared with the original method and with a linear programming algorithm (LPA) on accumulated-time and short-term measurement. The fluctuation of the modified method in the short-term experiment is 0.6 ppm (parts per million), which is obviously less than the 1.23 ppm and 1.45 ppm from the other two methods. DROML, when estimating a four-segment case, is able to output a skew of only 0.22 ppm error, compared with the result of the normal case.

Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS techniques) are strongly required in various applications. Both interconnection delays and clock skews have a large impact on circuit performance implemented onto FPGA, which indicates the need for floorplan-driven FPGA-HLS algorithms considering them. To appropriately estimate interconnection delays and clock skews at HLS phase, a reasonable model to estimate them becomes essential. In this paper, we demonstrate several experiments to characterize interconnection delays and clock skews in FPGA and propose novel estimate models called “IDEF” and “CSEF”. In order to evaluate our models, we integrate them into a conventional floorplan-driven FPGA-HLS algorithm. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 22% compared with conventional approaches.