Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering

Wei-Kai CHENG; Jui-Hung HUNG; Yi-Hsuan CHIU

doi:10.1587/transfun.E99.A.2388

Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering

Wei-Kai CHENG, Jui-Hung HUNG, Yi-Hsuan CHIU

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As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2388-2397

Publication Date: 2016/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E99.A.2388

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Authors

Wei-Kai CHENG
  Chung Yuan Christian University
Jui-Hung HUNG
  Chung Yuan Christian University
Yi-Hsuan CHIU
  Chung Yuan Christian University

Keyword

clock network synthesis, clock mesh, clock gating

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Wei-Kai CHENG, Jui-Hung HUNG, Yi-Hsuan CHIU, "Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering" in IEICE TRANSACTIONS on Fundamentals, vol. E99-A, no. 12, pp. 2388-2397, December 2016, doi: 10.1587/transfun.E99.A.2388.
Abstract: As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2388/_p

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@ARTICLE{e99-a_12_2388,
author={Wei-Kai CHENG, Jui-Hung HUNG, Yi-Hsuan CHIU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering},
year={2016},
volume={E99-A},
number={12},
pages={2388-2397},
abstract={As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.},
keywords={},
doi={10.1587/transfun.E99.A.2388},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2388
EP - 2397
AU - Wei-Kai CHENG
AU - Jui-Hung HUNG
AU - Yi-Hsuan CHIU
PY - 2016
DO - 10.1587/transfun.E99.A.2388
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.
ER -