As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.

Clock network synthesis is one of the most important and limiting factors in VLSI designs. Hence, the clock skew variation reduction is one of the most important objectives in clock distribution methodology. Cross-link insertion is proposed in [1], however, it is based on empirical methods and does not use variation information for link insertion location choice. [17] considers the delay variation, but it is slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Experimental results show that our algorithm is very fast and achieves better skew variability reduction while utilizing considerably lesser routing resources compared with existing methods.