Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion
Summary :
Clock network synthesis is one of the most important and limiting factors in VLSI designs. Hence, the clock skew variation reduction is one of the most important objectives in clock distribution methodology. Cross-link insertion is proposed in [1], however, it is based on empirical methods and does not use variation information for link insertion location choice. [17] considers the delay variation, but it is slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Experimental results show that our algorithm is very fast and achieves better skew variability reduction while utilizing considerably lesser routing resources compared with existing methods.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.1 pp.127-131
- Publication Date
- 2013/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.127
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
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Joon-Sung YANG, Ik Joon CHANG, "Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 1, pp. 127-131, January 2013, doi: 10.1587/transele.E96.C.127.
Abstract: Clock network synthesis is one of the most important and limiting factors in VLSI designs. Hence, the clock skew variation reduction is one of the most important objectives in clock distribution methodology. Cross-link insertion is proposed in [1], however, it is based on empirical methods and does not use variation information for link insertion location choice. [17] considers the delay variation, but it is slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Experimental results show that our algorithm is very fast and achieves better skew variability reduction while utilizing considerably lesser routing resources compared with existing methods.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.127/_p
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@ARTICLE{e96-c_1_127,
author={Joon-Sung YANG, Ik Joon CHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion},
year={2013},
volume={E96-C},
number={1},
pages={127-131},
abstract={Clock network synthesis is one of the most important and limiting factors in VLSI designs. Hence, the clock skew variation reduction is one of the most important objectives in clock distribution methodology. Cross-link insertion is proposed in [1], however, it is based on empirical methods and does not use variation information for link insertion location choice. [17] considers the delay variation, but it is slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Experimental results show that our algorithm is very fast and achieves better skew variability reduction while utilizing considerably lesser routing resources compared with existing methods.},
keywords={},
doi={10.1587/transele.E96.C.127},
ISSN={1745-1353},
month={January},}
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TY - JOUR
TI - Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion
T2 - IEICE TRANSACTIONS on Electronics
SP - 127
EP - 131
AU - Joon-Sung YANG
AU - Ik Joon CHANG
PY - 2013
DO - 10.1587/transele.E96.C.127
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2013
AB - Clock network synthesis is one of the most important and limiting factors in VLSI designs. Hence, the clock skew variation reduction is one of the most important objectives in clock distribution methodology. Cross-link insertion is proposed in [1], however, it is based on empirical methods and does not use variation information for link insertion location choice. [17] considers the delay variation, but it is slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Experimental results show that our algorithm is very fast and achieves better skew variability reduction while utilizing considerably lesser routing resources compared with existing methods.
ER -
English
