1-3hit |
Masayoshi OSHIRO Tatsuhiko MARUYAMA Takashi TOKAIRIN Yuki TUDA Tong WANG Naotaka KOIDE Yosuke OGASAWARA Tuan Thanh TA Hiroshi YOSHIDA Kenichi SAMI
A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2mA RX and 3.5mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture with high tolerance against out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of -93dBm and maximum output power of 0dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the minimum level of current consumption for both RX and TX modes in the published product-level SoCs.
Yosuke OGASAWARA Ryuichi FUJIMOTO Tsuneo SUZUKI Kenichi SAMI
A novel spur cancelled clock generator (SCCG) capable of recovering RX sensitivity degradations caused by digital clocks in wireless SoCs is presented. Clock spurs that degrade RX sensitivities are canceled by applying the SCCG to digital circuits or ADCs. The SCCG is integrated into a Bluetooth Low Energy (BLE) SoC fabricated in a 65 nm CMOS process. A measured clock spur reduction of 34 dB and an RX sensitivity recovery of 5 dB are achieved by the proposed SCCG. The power consumption and occupied area of the SCCG is only 18 µW and 40 μm × 120 μm, respectively.
Daisuke MIYASHITA Kenichi AGAWA Hirotsugu KAJIHARA Kenichi SAMI Ichiro SETO Ryuichi FUJIMOTO Yasuo UNEKAWA
TransferJetTM is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer up to 522 Mbps within a few centimeters range. We present a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz signal bandwidth using a 65 nm CMOS technology. Baseband filtering techniques for a transmitter (TX) and a receiver (RX) are proposed in order to handle the ultra-wide bandwidth with low power consumption and small area. A programmable power attenuator (PAT) for precise output power is also proposed in this paper. The SoC achieves energy efficiencies of 0.19 nJ/bit and 0.43 nJ/bit for the TX and the RX, respectively. The RX sensitivity of -70 dBm for 522 Mbps data rate and the TX error vector magnitude (EVM) of -31 dB are achieved.