The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

TransferJetTM is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer up to 522 Mbps within a few centimeters range. We present a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz signal bandwidth using a 65 nm CMOS technology. Baseband filtering techniques for a transmitter (TX) and a receiver (RX) are proposed in order to handle the ultra-wide bandwidth with low power consumption and small area. A programmable power attenuator (PAT) for precise output power is also proposed in this paper. The SoC achieves energy efficiencies of 0.19 nJ/bit and 0.43 nJ/bit for the TX and the RX, respectively. The RX sensitivity of -70 dBm for 522 Mbps data rate and the TX error vector magnitude (EVM) of -31 dB are achieved.