The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

As a first step towards the realization of high-efficiency on-chip antennas for 60GHz-band wireless personal area networks, this paper proposes the fabrication of a patch antenna placed on a 200µm thick dielectric resin and fed through a hole in a silicon chip. Despite the large tan δ of the adopted material (0.015 at 50GHz), the thick resin reduces the conductor loss at the radiating element and a radiation efficiency of 78%, which includes the connecting loss from the bottom is predicted by simulation. This calculated value is verified in the millimeter-wave band by experiments in a reverberation chamber. Six stirrers are installed, one on each wall in the chamber, to create a statistical Rayleigh environment. The manufactured prototype antenna with a test jig demonstrates the radiation efficiency of 75% in the reverberation chamber. This agrees well with the simulated value of 76%, while the statistical measurement uncertainty of our handmade reverberation chamber is calculated as ±0.14dB.

For the realization of a high-efficiency antenna for 60GHz-band wireless personal area network, we propose placing a CMOS RF circuit and an antenna on opposing sides of a silicon chip. They are connected with low loss by a coaxial-line structure using a hole opening in the chip. Since the CMOS circuit is driven differentially, a differential-feed antenna is used. In this paper, we design and measure a differential-feed square patch antenna on a silicon chip. To enhance the radiation efficiency, it is placed on a 200µm thick resin layer. The calculated radiation efficiency of 79% includes the connection loss. A prototype antenna is measured in a reverberation chamber, and its radiation efficiency is estimated to be about 81±3%.