Look Up Table Compaction Based on Folding of Logic Functions
Summary :
The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2701-2707
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
Authors
Keyword
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Shinji KIMURA, Atsushi ISHII, Takashi HORIYAMA, Masaki NAKANISHI, Hirotsugu KAJIHARA, Katsumasa WATANABE, "Look Up Table Compaction Based on Folding of Logic Functions" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2701-2707, December 2002, doi: .
Abstract: The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2701/_p
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@ARTICLE{e85-a_12_2701,
author={Shinji KIMURA, Atsushi ISHII, Takashi HORIYAMA, Masaki NAKANISHI, Hirotsugu KAJIHARA, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Look Up Table Compaction Based on Folding of Logic Functions},
year={2002},
volume={E85-A},
number={12},
pages={2701-2707},
abstract={The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Look Up Table Compaction Based on Folding of Logic Functions
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2701
EP - 2707
AU - Shinji KIMURA
AU - Atsushi ISHII
AU - Takashi HORIYAMA
AU - Masaki NAKANISHI
AU - Hirotsugu KAJIHARA
AU - Katsumasa WATANABE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
ER -
English
