A statistic based algorithm for watermarking 2D vector maps is proposed. Instead of 2D coordinates, a one-dimensional distance sequence extracted from the original map is used as the cover data to achieve the shape-preserving ability. The statistical feature of the cover data is utilized for data embedding. Experiment results indicate the scheme's better performance in invisibility, as well as its robustness to certain attacks.

A four-stage power amplifier (PA) with 10 GHz 1-dB bandwidth (56–66 GHz) is presented. The broadband performance is achieved owing to π-section interstage matching network. Three-stage-current-reuse topology is proposed to enhance efficiency. The amplifier has been fabricated in 65 nm digital CMOS. 18 dB power gain and 9.6 dBm saturated power (Psat) are achieved at 60 GHz. The PA consumes current of 50 mA at 1.2 V supply voltage, and has a peak power-added efficiency (PAE) of 13.6%. To the best of the authors' knowledge, this work shows the highest PAE among the reported CMOS PAs that covers the worldwide 9 GHz ISM millimeter-wave band with less-than-1.2 V supply voltage.

We report a new approach to creating a 'solid ink' and direct patterning of InAs nanowires on a Si substrate using dip-pen nanolithography (DPN). The normal method to prepare an 'ink' is a solution-based process using sonication to liquidize nanoparticles, which we call 'liquid ink' in this paper. As ink-solution-based DPN patterning has been prevalent in most studies, herein we propose a new method, 'solid inking', by which the inking process is solution-free. In our work, InAs nanowires were transferred to an AFM tip by directly scanning the tip over an InAs nanowire wafer at humidity over 80%. By this method, the preparation of ink and the 'inking' process is combined into one step, and a large amount of nanowires can be collected onto the tip to ensure the formation of a continuous ink flow for the direct patterning.

A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2mA RX and 3.5mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture with high tolerance against out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of -93dBm and maximum output power of 0dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the minimum level of current consumption for both RX and TX modes in the published product-level SoCs.