This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

A DC offset caused by self-mixing is a serious problem for direct-conversion receivers. Local oscillation (LO) leakage via quadrature demodulators (QDEMOD) must be suppressed in order to achieve a low DC offset. An LO buffer which drives QDEMOD mainly causes the LO leakage. We proposed an LO buffer which has a high-pass frequency response with small occupied area and low current consumption. A QDEMOD using the proposed LO buffer is fabricated using a SiGe BiCMOS process. Measured low LO leakage of -70 dBm is achieved, which is 10 dB lower than that of a QDEMOD with a conventional LO buffer. This measured result indicates that the proposed LO buffer is suitable for QDEMODs for direct-conversion receivers.

A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 8040 µm2. The active area of the PLL is 0.31 mm2.

A four-stage power amplifier (PA) with 10 GHz 1-dB bandwidth (56–66 GHz) is presented. The broadband performance is achieved owing to π-section interstage matching network. Three-stage-current-reuse topology is proposed to enhance efficiency. The amplifier has been fabricated in 65 nm digital CMOS. 18 dB power gain and 9.6 dBm saturated power (Psat) are achieved at 60 GHz. The PA consumes current of 50 mA at 1.2 V supply voltage, and has a peak power-added efficiency (PAE) of 13.6%. To the best of the authors' knowledge, this work shows the highest PAE among the reported CMOS PAs that covers the worldwide 9 GHz ISM millimeter-wave band with less-than-1.2 V supply voltage.

A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using a common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for integrating on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to DC current increase and intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using SiGe BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -10 dBm.

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, low-pass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.