A linear-in-dB VGA of the current-divider type is fabricated in 0.25 µm CMOS technology. Two gain compensation techniques are proposed in order to compensate the gain deviations due to a MOSFET which has a square-law characteristic or an exponential-law characteristic determined by its current density. Temperature compensation techniques are also proposed. Measure results obtained at 380 MHz are a gain range of 80 dB, a gain error of 3 dB, and an NF of 11 dB.

A DC offset caused by self-mixing is a serious problem for direct-conversion receivers. Local oscillation (LO) leakage via quadrature demodulators (QDEMOD) must be suppressed in order to achieve a low DC offset. An LO buffer which drives QDEMOD mainly causes the LO leakage. We proposed an LO buffer which has a high-pass frequency response with small occupied area and low current consumption. A QDEMOD using the proposed LO buffer is fabricated using a SiGe BiCMOS process. Measured low LO leakage of -70 dBm is achieved, which is 10 dB lower than that of a QDEMOD with a conventional LO buffer. This measured result indicates that the proposed LO buffer is suitable for QDEMODs for direct-conversion receivers.

A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.

A direct conversion receiver IC including an on-chip balun, an I/Q mixer, a variable gain amplifier and a 90 phase-shifter is fabricated in a Bi-CMOS technology with 15 GHz transition frequency (fT). This paper demonstrates that cascaded connection of an on-chip balun and a double balanced mixer as the I/Q mixer is effective to achieve a low DC offset and a low second-order distortion, on the basis of both careful examination of the mixer behavior and measurement. Input-referred DC offset voltage of less than 300 µV and spurious free dynamic range (SFDR) of over 67 dB are obtained by measurement. The IC consumes 52 mA from 2.7 V power supply voltage. The die size is 3 mm 3 mm.

We have developed a GaAs direct-conversion π/4 shifted QPSK modulator IC equipped with variable attenuators for controlling the output power level of the 1.9 GHz Personal Handy Phone system in Japan (PHS). The IC was successfully demonstrated showing state-of-the-art performance with the image rejection ratio of more than 36 dBc at a low input power of -10 dBm in 1.9 GHz frequency range. By using the "Gate Current Control method by Pull-down FET's" (GCCPF), the equipped attenuators vary the output power from 0 dB to -28 dB by 4 dB step. The IC operates at a 2.7 V supply with power dissipation of 259 mW. The 2.64.6 mm2 chip with about 400 elements was fabricated by a 0.5 µm WNx-gate BPLDD GaAs MESFET process.

A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.

This paper describes a low-power-supply 2-GHz CMOS up-converter. A current-mode mixing method using current adding and self-switching mixers is proposed for 1-V operation. The current-mode up-converter achieves conversion gain of 6.7 dB and linearity of 6.5-dBm OIP3 at 1 V. Balanced configuration and DC offset canceller reduce LO leakage below -40 dBc even with 20-mV Vth mismatches. The bias circuit of the IC is designed to maintain constant conversion gain for variation of temperature for practical usage. The measurement results indicate the proposed up-converter is applicable for future wireless systems.

A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with fT of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.

Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.

This paper presents a 1024-QAM OFDM signal capable WLAN receiver in 65nm CMOS technology. Thermal noise-based IQ frequency-independent mismatch correction and IQ frequency-dependent mismatch correction with baseband loopback are proposed for the self-calibration in the receiver. The measured image rejection ratio of the self-calibration is -56.3dB. The receiver achieves the extremely low EVM of -37.1dB even with wide channel bandwidth of 80MHz and has the ability to receive the 1024-QAM signal. The result indicates that the receiver is extendable for the 802.11ax compliant receiver that supports a higher density modulation scheme of MIMO.