A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler

Shoji OTAKA; Ryuichi FUJIMOTO; Hiroshi TANIMOTO

A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler

Shoji OTAKA, Ryuichi FUJIMOTO, Hiroshi TANIMOTO

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A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with f_T of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.2 pp.313-319

Publication Date: 1999/02/25

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Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Shoji OTAKA, Ryuichi FUJIMOTO, Hiroshi TANIMOTO, "A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler" in IEICE TRANSACTIONS on Fundamentals, vol. E82-A, no. 2, pp. 313-319, February 1999, doi: .
Abstract: A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with f_T of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_313/_p

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@ARTICLE{e82-a_2_313,
author={Shoji OTAKA, Ryuichi FUJIMOTO, Hiroshi TANIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler},
year={1999},
volume={E82-A},
number={2},
pages={313-319},
abstract={A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with f_T of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 313
EP - 319
AU - Shoji OTAKA
AU - Ryuichi FUJIMOTO
AU - Hiroshi TANIMOTO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with f_T of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.
ER -