This paper describes design considerations for high frequency active BPFs up to 100 MHz. The major design issues for high frequency active filters are the excess phase shift in the integrators and high power consumption of the integrators. Typical bipolar transistor based transconductors such as the Gilbert gain cell and the linearized transconductor with two asymmetric emitter-coupled pairs have been analyzed and compared. It has been clarified that the power consumption of the linearized transconductor can be much smaller than that of the Gilbert gain cell because of its high transconductance to working current ratio while maintaining a signal to noise ratio of the same order. A simple high-speed fully differential linearized transconductor cell is proposed with emitter follower buffers and resistive loads for excess phase compensation. A novel gyrator based transformation for the LC ladder BPF has been introduced. This transformation has resulted in a structure with simple capacitor-coupled active resonators which exactly preserves the original transfer function. A fourth order 10.7 MHz BPF IC was designed using the proposed transconductors. It was fabricated and has demonstrated the usefulness of the proposed approach. In addition, an experimental 100 MHz second order BPF IC with Q=14 has been successfully implemented indicating the potential of the proposed approach.

A miniature transceiver, including highly integrated MMIC front-end, for 1.9 GHz band personal handy phone system(PHS) has been developed. The terminal, adopting direct conversion transmitter and receiver technology, consists of four high-density RF circuit modules and a digital signal processing LSI with 2.7 V power supply. The four functional modules are a power amplifier, a transmitter,a receiver, and a frequency synthesizer. Each functional module includes one IC chip and passive LCR components connected with solder bumps on module substrate. The experimental miniature PHS handset has been fabricated to verify the design concepts of the miniature transceiver. The total volume of the developed PHS terminal is 60cc, including the 12cc front-end which comprises the four RF functional circuit modules. The air interface connection with the PHS base station simulator has been confirmed.

A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.

Simple and scalable device-modeling techniques for inductors and capacitors are described. All model parameters are calculated from geometric parameters of the device, process parameters of the technology, and a substrate resistance parameter. Modeling techniques for other devices, such as resistors, varactor diodes, pads and MOSFETs, are also described. Some simulation results using the proposed device-modeling techniques are compared with measured results and they indicate adequacy of the proposed device-modeling techniques.

Determination of wordlength is essential for designing digital circuits because the wordlength affects system performance, hardware size, and power consumption. Variable wordlength methods that a system dynamically and effectively changes the wordlength depending on surrounding environments have been studied for power reduction in wireless systems. The conventional variable wordlength methods induce communication performance degradation when compared with a floating-point representation in time-varying fading channels. This paper discusses rapid wordlength control on packet basis and proposes a new method based on monitoring subcarrier SNRs in an OFDM receiver. The proposed method can estimate signal quality accurately and can decrease the wordlength decision errors. The simulation results have indicated that the proposed method shows better PER performance compared with the conventional methods.

This paper describes a numerical design procedure of element values of RC polyphase filters with equal minima in stopband and equal ripple in passband. Determination of element values of RC polyphase filters with equal-ripple characteristic have not been solved to the best knowledge of the authors. There found a paper tackling with the problem; however, it can only give sub-optimal solutions via numerical calculation [3]. We propose a numerical element value design procedure for RC polyphase filters with equi-ripple gain in both stopband and passband by using the coefficient matching method. Some design examples are given.

This paper presents analysis and design of passive RC polyphase filters (RCPFs) in tutorial style. Single-phase model of a single-stage RCPF is derived, and then, multi-stage RCPFs are analyzed and obtained some restrictions for realizable poles and zeros locations of RCPFs. Exact design methods of RCPFs with equal ripple type, and Butterworth type responses are explained for transfer function design and element value design along with some design examples.

A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.

This paper presents a 1 V operating fully differential OTA using NMOS inverters in place of the traditional differential pair. To obtain high gain, a two-stage configuration is used in which the first stage has feedforward paths to cancel the common-mode signal, and the second stage has common-mode feedback paths to stabilize the output common-mode voltage. The proposed OTA was fabricated by an 0.18 µm CMOS technology. Measured gain is 40 dB and GBW is 10 MHz, in addition to differential output voltage swing of 1.8 Vp - p. It is confirmed that the proposed OTA can operate from 1 V power supply and has very large output swing capability even in a 1 V operation. The proposed OTA configuration contributes to a solution to the low power supply voltage issue in scaled CMOS analog circuits.

A broadband and flexible receiver architecture is investigated for the handheld software defined radio (SDR). The proposed SDR architecture is based on the direct conversion and low intermediate frequency (low-IF) principle with digital channel filtering, which provides the receiver with flexibility for the multi-standard application. This architecture also enables analog-to-digital converter activating essentially in baseband or low frequency so that the clock jitter, which serves as an important subject in the well-known IF sampling method, can be reduced. Basic performance of the proposed architecture has been confirmed by the experimental model.

Element value spread of an equal-ripple RC polyphase filter depends heavily on the order of zero assignment. To find the optimum design, we must conduct exhaustive design for all the possible zero assignments. This paper describes two circuit transformations on equal-ripple RC polyphase filters, which preserve their transfer functions, for reducing circuit design efforts. Proposed Method I exchanges (R,C) values to (1/C,1/R) for each stage. This gives a new circuit with different zero assignment for each stage of its original circuit. Method II flips over the original circuit and exchanges the resulting (Ri,Ci) values for (Cn-i+1,Rn-i+1) for each i-th stage. Those circuit transformations can reduce a number of circuit designs down to 1/4 of the straight-forward method. This considerably reduces a burden for exhaustive design for searching the minimum element value spread condition. Some design examples are given to illustrate the proposed methods.

A direct conversion receiver IC including an on-chip balun, an I/Q mixer, a variable gain amplifier and a 90 phase-shifter is fabricated in a Bi-CMOS technology with 15 GHz transition frequency (fT). This paper demonstrates that cascaded connection of an on-chip balun and a double balanced mixer as the I/Q mixer is effective to achieve a low DC offset and a low second-order distortion, on the basis of both careful examination of the mixer behavior and measurement. Input-referred DC offset voltage of less than 300 µV and spurious free dynamic range (SFDR) of over 67 dB are obtained by measurement. The IC consumes 52 mA from 2.7 V power supply voltage. The die size is 3 mm 3 mm.

A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.

A fully balanced (FB) transconductor using two multi-input single-ended (SE) CMOS transconductors is proposed, where the transconductors use MOS transitors operating in a triode region for achieving a wide linear input-range. SE circuits are easier to design than differential circuits and inherently reject common-mode (CM) signals. The multi-input structure is used to make a CM feedback loop and to determine an output CM voltage. A high-output-resistance current mirror is used in converting a differential signal to a single-ended signal in order to achieve a high common-mode rejection ratio (CMRR) and a high output-resistance of the transconductor. The FB transconductor achieves a 2-Vpp linear input range at a 2.5-V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with a linear input-range of 1.2 Vpp and at 1.6 V with a linear input-range of 0.9 Vpp. A 2.5-V 2.5-MHz FB Gm-C filter using the FB transconductors achieved a CMRR of 45 dB and a passband IIP3 of 32 dBm.

An architecture for a digital-to-RF converter for a software defined radio (SDR) transmitter is proposed. The ideal hardware architecture for an SDR is a digital-signal to RF-signal direct conversion transmitter. However no conventional digital-to-analog converter (DAC) has converted over 1-GHz RF signal with enough resolution, in the present condition. In this paper, a digital-to-RF direct converter architecture using a ΔΣ modulation technique is proposed for the amplitude-phase modulated signal. The experimental results show that the proposed direct converter outputs a sufficiently accurate signal.

This paper presents a very wideband active RC polyphase filter (ARCPF). We propose a unit section of the ARCPF, which is an ordinary RCPF followed by opamps with parallel RC feedback. In the proposed unit section, pole and zero can be assigned independently. By using the unit ARCPFs, a very wideband image rejection filter can be realized by cascading the sections, which can greatly reduce the element value spread. To realize this, CMOS inverter based fully differential OTA which can operate under low supply voltage is also presented. This paper describes a six-stage active RC polyphase filter with 1-100 MHz passband in 0.18 µm CMOS technology.

This paper describes a method to distinguish phase noise and amplitude noise from total oscillator noise in circuit simulation, and derives general relationships between periodic time-varying transfer functions for oscillators and phase and amplitude noises.